Abstract: A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.

Abstract: A permutation instruction generates vector elements for a destination register using identified source and destination registers. A plurality of partial table lookups corresponding to an extended table produces a plurality of intermediate results. At least one source register stores a plurality of index values corresponding to the extended table. Out-of-range index values are values that are not contained in at least one additional source register and result in a predetermined constant value being stored into a predetermined vector element of the destination register. The index values are adjusted between the partial table lookups. A final result is formed by performing a logic function with the plurality of intermediate results. The final result is thereby formed without a full table lookup of each element of the final result.

Abstract: An integrated circuit for detecting a bonding defect in a multi-bonding wire. The integrated circuit includes a plurality of pads each connectable by a bonding wire to a lead terminal. Voltage supplied to the lead terminal is applied in common to the plurality of pads. A detection circuit is operably connected to the plurality of pads. The detection circuit detects breakage of the bonding wires based on potentials at the plurality of pads.

Abstract: A multi-user multiple input multiple output (MIMO) downlink beamforming system with limited feed forward (200) is provided to enable precoding matrix information to be efficiently provided to a subset of user equipment devices (201.i), where zero-forcing transmit beamformers (wi) are computed at the base station (210) and assembled into a precoding matrix (W). The precoding matrix is encoded using a compact reference signal codebook (225, 207.i) for forward link signaling, either by sending bits indicating the index of the transmission matrix used, or by transmitting one or more precoded pilots or reference signals wherein the pilot signals are precoded using vectors uniquely representative of the transmission matrix used which includes candidate reference signal matrices which meet a predetermined condition number requirement, such as a condition number threshold.

Abstract: A system that includes a first flip flop that is serially coupled to a second flip flop. The first flip flop includes a transfer circuit that is coupled between a master latch and a slave latch. The master latch of the first flip flop latches a scan data signal during a first portion of a cycle of a first clock signal that is provided to the first flip flop. The transfer circuit is conductive during a sub-portion of a second portion of the cycle of the first clock signal. The sub-portion starts after an occurrence of a predefined change in a control signal provided to the slave latch. The predefined change occurs after an estimated start of a first portion of a cycle of a second clock signal that is provided to the second flip flop. A master latch of the second flip flop latches the scan data signal during a first portion of a next cycle of the second clock signal.

Abstract: A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.

Abstract: A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die.

Abstract: A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.

Abstract: A voltage regulator comprising at least first and second regulator elements connected between an output node and a supply rail for supplying load current to a load connected to the output node. The voltage regulator comprises first and second control modules for controlling the first and second regulator elements respectively to maintain the output node at a regulated voltage in the presence of a variable impedance presented by the load to the output node, the second regulator element and the second control module having a smaller load current capacity and smaller leakage current than the first regulator element and the first control module.

Abstract: An embodiment of a baseband filter in a transmitter subsystem of a wireless device comprises an operational amplifier (op-amp), a pole circuit, a feedback capacitor, and an active device. The op-amp is adapted to produce an amplified signal that includes noise gain produced by the op-amp. The pole circuit is electrically coupled with an output terminal of the op-amp, and is adapted to receive the amplified signal and to attenuate the noise gain to produce a filtered, amplified signal. The feedback capacitor is electrically coupled between the first pole circuit and an input terminal of the op-amp, and is adapted to compensate for a phase shift produced by the pole circuit. The active device is electrically coupled with the pole circuit, and is adapted to amplify the filtered, amplified signal and to produce a baseband filtered output signal.

Abstract: Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

Abstract: A differential amplifier that has a current supply and a differential current to voltage converter with a positive current input node, a negative current input node and a voltage output node, has offset voltage trimming. The voltage output node provides an output voltage that is proportional to the difference in current values flowing into the positive current input node and a negative current input node. A trimming circuit has a plurality of trimming control inputs, an inverting trimming output, a non-inverting trimming output and trimming inputs coupled to the current supply. Trimming resistances couple the inverting trimming output to the non-inverting trimming output. Trimming selectors, controllable by a trim code provided to the trimming control inputs, provide for selectively connecting the current supply directly to the non-inverting trimming output while selectively connecting the current supply to the inverting trimming output through a first selected group of the trimming resistances.

Abstract: A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.

Abstract: A system (100, FIG. 1) performs digital pre-distortion using gain values stored in a lookup table (150). A method for performing digital pre-distortion includes identifying (310, FIG. 3) a lookup table entry, based on input data, and updating the lookup table entry by writing an updated gain value into the lookup table entry. In an embodiment, update tracking information corresponding to the lookup table entry may be updated (324) to indicate that the lookup table entry has been updated. Another embodiment includes identifying (412, FIG. 4) consecutive lookup table entries based on input data, determining (413) whether the consecutive lookup table entries have been previously updated, and performing (414) a weighted interpolation process to produce an output gain value. A previous gain value (158, FIG. 1) is used in the weighted interpolation process when at least one of the consecutive lookup table entries has not been updated.

Abstract: A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

Abstract: A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.

Abstract: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Abstract: A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage.