Abstract: An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.

Abstract: A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronizing means for each of the groups, using the synchronizing means to synchronize the data in each group, and transmitting the data to a recipient characterized in that the data is divided in accordance with its synchronization requirements with the recipient.

Abstract: A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.

Abstract: A mold (10) including a first mold part (12) and a second mold part (14) define a mold cavity (16) therebetween. A gate (18) is formed in at least one of the first and second mold parts (12) and (14) such that the gate (18) communicates with the mold cavity (16). A vent (20) having a constricted portion (22) is arranged to communicate with the mold cavity (16). A substrate (28) including a base substrate (30) and an electrically conductive pattern (32) and (34) formed on the base substrate (30) may be received in the mold (10). A solder resist layer (36) is formed on the base substrate (30) and a portion of the electrically conductive pattern (32). A plurality of grooves (38) and (40) is formed in a staggered arrangement around a periphery of a molding area (42) on the substrate (28).

Abstract: In a data processing system, an address associated with a processing operation is received. A modified address is generated which includes a characteristic indicator within the address at a first predetermined bit position when the characteristic indicator is of a first type or at a second predetermined bit position when the characteristic indicator is of a second type. A first value of the characteristic indicator indicates a characteristic of the address. A modified address may also be generated which includes a characteristic indicator at a first predetermined bit position when a position indicator has a first value or at a second predetermined bit position when the position indicator has a second value. Address information can then be generated from the modified address, and a debug message can be created which includes the address information.

Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Abstract: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer.

Abstract: A temperature estimation circuit for estimating a temperature of an integrated circuit die comprises a temperature increase estimation circuit, the circuit has one or more inputs operable to receive one or more notification signals corresponding to command signals passed to the integrated circuit, and an output providing a sum of one or more temperature increase values, corresponding to temperature increase of the integrated circuit due to one of the command signals. The circuit may further have a temperature decrease estimation circuit, comprising an input operable to receive a calculated die temperature value, and an output providing a temperature decrease value depending on a mathematical model of temperature decrease when no command signal is applied.

Abstract: A voltage controlled oscillator circuit comprises a VCO resonator circuit having a first plurality of varactors for varying a frequency of the VCO resonator circuit the VCO resonator circuit being symmetrical with respect to VCO circuit ground and providing a signal having a frequency, the frequency depending on a tuning voltage applied to the first plurality of varactors, and a second plurality of varactors for compensating a drift of the frequency depending on a compensation voltage, a temperature sensor circuit sensing an ambient temperature of the VCO resonator circuit and providing a temperature dependent signal, and a temperature compensation circuit providing the compensation voltage depending on the temperature dependent signal. Furthermore, a phase locked loop (PLL) circuit, an automotive radar device and a method for compensating a frequency drift of a VCO resonator circuit are presented.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

Abstract: A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage.

Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional resist openings (119) formed over inactive areas (15) in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings (119) are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g., 152) for use in manufacturing the final structure.

Abstract: A wordline driver, for a non-volatile memory device, comprises a wordline driver output, a first power source, adapted to provide an erase level voltage for erasing portions of the non-volatile memory device, a second power source, adapted to provide read and program level voltages for reading and programming portions of the non-volatile memory device and first switching means, including an isolation transistor, adapted to connect the wordline driver output to a one of the first and second power sources dependent upon an operating mode of the wordline driver. The wordline driver further comprises a programmable switch controller for providing a variable control signal to a control electrode of the isolation transistor. The programmable switch controller is arranged to set the variable control signal to a value dependent upon the operating parameters of the non-volatile memory device and such that the endurance of the isolation transistor is maximised.

Abstract: A processing system includes a processing module and a memory module for storing plurality of data. A controllable power source supplies a source voltage to the memory module in response to a target voltage. A controller module receives a temperature signal and adjusts the target voltage in response to the temperature signal.

Abstract: A down-conversion module for a heterodyne receiver comprises a first mixer circuit, a second mixer circuit and an interconnection. The first mixer circuit includes first and second differential control terminals and is arranged to produce a first down-converted differential voltage signal at a first down-converted frequency as a function of a first RF differential input signal applied to the first differential control terminals and of a first RF differential reference frequency signal applied to the second differential control terminals.

Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.

Abstract: An integrated circuit comprises a receiver and an oscillator circuit. The receiver has a first input port for receiving a first oscillatory input signal, a second input port for receiving a second oscillatory input signal, and an output port for delivering an oscillatory output signal which is a function of both the first input signal and the second input signal. The oscillator circuit has a first output port for delivering a first oscillatory signal, and a second output port for delivering a second oscillatory signal. The first output port of the oscillator circuit is coupled to the HF port, and the second output port of the oscillator circuit is coupled to the LO port. The integrated circuit may be designed such that the HF port may be disconnected from the first output port of the oscillator circuit without affecting the operability of the receiver. An apparatus for testing the proper functioning of an integrated circuit as described above and a method of producing a receiver are also disclosed.

Abstract: A data communication method is provided, comprising: processing high-speed digital data for communication to produce processed data; generating short impulse wavelets; constructing a digitally modulated ultra wideband signal from the short impulse wavelets in response to bits of the processed data, wherein the digitally modulated ultra wideband signal comprises a series of the short impulse wavelets, and the value of each bit of the processed data is digitally modulated onto the shape of at least one of the short impulse wavelets of the series, to produce a series of digitally shape modulated impulse wavelets; and transmitting the digitally modulated ultra wideband signal, including the series of digitally shape modulated impulse wavelets, via an antenna.

Abstract: Embodiments include methods and apparatus for performing capacitive touch sensing and proximity detection. Electrode selection circuitry establishes a first connection with an individual electrode of a plurality of individual electrodes in order to receive one or more first signals indicating a state of the individual electrode, and establishes second connections with a proximity electrode that comprises multiple ones of the plurality of individual electrodes in order to receive one or more second signals indicating a state of the proximity electrode. A processing system performs a first analysis on the first signals to determine whether to perform a first updating process for an individual electrode baseline value, and performs a second analysis on the second signals to determine whether to perform a second updating process for a proximity electrode baseline value. In an embodiment, the first analysis and the second analysis are different from each other.

Abstract: A bandgap voltage reference unit on an integrated circuit (101) includes a proportional-to-absolute-temperature (PTAT) current source (100) coupled to a bandgap voltage reference circuit (200) that includes a plurality of self-cascode MOSFET structures (201-204) that are cascaded together to form a PTAT voltage generator (205). The bandgap voltage reference circuit also includes a complementary-to-absolute-temperature (CTAT) device (260). A PTAT voltage from the PTAT voltage generator is added to a CTAT voltage from the CTAT device to produce an output voltage of the bandgap voltage reference unit, such that the output voltage is the bandgap voltage of the integrated circuit and such that the output voltage does not change with temperature.