Patents Assigned to Freescale
  • Publication number: 20100268905
    Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.
    Type: Application
    Filed: December 17, 2007
    Publication date: October 21, 2010
    Applicants: Freescale semiconductor, Inc., Continental Teves AG & Co. oHG
    Inventors: Anthony Reipold, Houman Amjadi, Lukusa D. Kabulepa, Andreas Kirschbaum, Adrian Traskov
  • Patent number: 7818613
    Abstract: An arrangement and method for interconnecting fail-uncontrolled processor nodes in a dependable distributed system. A node has a bus guardian with input switches which act in combination with a logic element as an input multiplexer under the control of a control unit. This provides the advantage of transferring the problem of fault containment from the output interface of a potentially faulty processing node to the input interface of fault-free processing nodes. By doing so, problems encountered by spatial proximity faults or functional dependencies within a faulty processing node that may jeopardize fault containment at its output interface are mitigated.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Christopher Temple
  • Patent number: 7816948
    Abstract: A voltage translator having an input which receives an input signal and an output which provides a level shifted output signal includes a first inverter having an input coupled to receive the input signal, a second inverter having an input coupled to an output of the first inverter, a third inverter having an input coupled to an output of the second inverter, a fourth inverter having an input coupled to receive the input signal and an output coupled to an output of the third inverter, a fifth inverter having an input coupled to an output of the fourth inverter and having an output coupled to the input of the third inverter, and a sixth inverter having an input coupled to the output of the fifth inverter and an output coupled to the output of the voltage translator. The second and fourth inverters are coupled to a calibration voltage supply terminal.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Hector Sanchez
  • Patent number: 7817807
    Abstract: An audio output driver includes an audio amplifier for generating an amplified signal. A virtual ground generator generates a virtual ground signal in response to a virtual ground reference. A combiner produces an output signal, based on the amplified signal and the virtual ground signal, that is coupled to an audio output device. A voltage equalizer equalizes the virtual ground reference and the output signal when the supply voltage compares unfavorably to a supply voltage threshold.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ajaykumar Kanji
  • Patent number: 7816221
    Abstract: High frequency performance of (e.g., silicon) bipolar devices (40, 100, 100?) is improved by reducing the capacitive coupling (Cbc) between the extrinsic base contact (46) and the collector (44, 44?, 44?). A dielectric ledge (453, 453?) is created during fabrication to separate the extrinsic base contract (46) from the collector (44, 44?, 44?) periphery (441). The dielectric ledge (453, 453?) underlies the transition region (461) where the extrinsic base contact (46) is coupled to the intrinsic base. (472) During device fabrication, a multi layer dielectric stack (45) is formed adjacent the intrinsic base (472) that allows the simultaneous creation of an undercut region (457, 457?) in which the intrinsic base (472) to extrinsic base contact (46) transition region (461) can be formed.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner
  • Patent number: 7817466
    Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 19, 2010
    Assignees: STMicroelectronics (Crolles 2) SAS, Freescale Semiconductor, Inc.
    Inventors: Richard Ferrant, Franck Genevaux, David Burnett, Gerald Gouya, Pierre Malinge
  • Patent number: 7818720
    Abstract: A method, computer program product, and data processing system for performing automated optimization of a control processing flow containing Boolean conditional expressions is disclosed. Each conditional expression is profiled using a representative set of test vectors to determine the probabilities of individual conditions and combinations of conditions in the expression. Next, the expression is restructured or reordered, including selective computation of subexpressions, based on the probability information, so as to maximize the probability of a short-circuit termination of evaluation of the expression and/or to minimize the statistical execution time of the expression. This process is performed for all Boolean conditional expressions related to the control processing flow.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kim-Chyan Gan, Lucio F. C. Pessoa, Wen Wu Su
  • Patent number: 7817387
    Abstract: An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael G. Khazhinsky, Leo Mathew, James W. Miller
  • Patent number: 7816211
    Abstract: A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Ramachandran Muralidhar
  • Publication number: 20100259318
    Abstract: A device (110) includes a sensing element (26) having drive nodes (34, 36) and sense nodes (42, 44). Parasitic capacitance (22) is present between drive node (34) and sense node (42). Likewise, parasitic capacitance (24) is present between drive node (36) and sense node (44). When a drive signal (56) is applied between drive nodes (34, 36), a parasitic current (70) between drive and sense nodes (34, 42) and a parasitic current (72) between drive and sense nodes (36,44) is created due to the parasitic capacitances (22, 24). A capacitive network (112) is coupled between the drive node (36) and the sense node (42) to create a correction current (134) through capacitive network (112) that cancels parasitic current (70). Likewise, a capacitive network (114) is coupled between the drive node (34) and the sense node (44) to create a correction current (138) through capacitive network (112) that cancels parasitic current (72).
    Type: Application
    Filed: April 9, 2009
    Publication date: October 14, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: David E. Bien, Dejan Mijuskovic
  • Publication number: 20100263043
    Abstract: A device includes a first test port coupled to a first test device, a second test port coupled to a second test device, a resource, and a security controller coupled to the first and second test ports. The security controller is operable to authenticate the first test device prior to authenticating the second test device, and, in response to authenticating the first test device, permit the first and second test devices to access the first resource.
    Type: Application
    Filed: April 9, 2009
    Publication date: October 14, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Zheng Xu
  • Patent number: 7812448
    Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24).
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
  • Patent number: 7813908
    Abstract: A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock control model. Accordingly, the simulated power state of the portion of the integrated circuit model to be clocked by a clock control model can be monitored based on the indicator from the clock control model, rather than on a higher level analysis of the simulated input/output behavior of the integrated circuit model.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jen-Tien Yen, Jeff B. Golden, Richard G. Woltenberg
  • Patent number: 7811932
    Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Scott K. Pozder, Ritwik Chatterjee
  • Patent number: 7813455
    Abstract: A MIMO wireless communication system and method reduces the number of recursive operations when decoding received data symbols by decoding the data symbols in pairs rather than on a per symbol basis. Decoding in pairs is facilitated by the determination that errors between selected pairs of data symbols are uncorrelated and identically distributed with a determined variance. Additionally, the system and method can order the pairs and provide decoding rules that result in an insignificant loss of performance for a wide range of signal-to-noise ratios (SNRs). Furthermore, the system and method exploit the structure of the error covariance matrix to reduce computational demands.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jayesh H. Kotecha
  • Patent number: 7811886
    Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Rajesh A. Rao, Sung-Taeg Kang, Ko-Min Chang, Jane Yater
  • Patent number: 7811382
    Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
  • Patent number: 7811889
    Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal P. Trivedi, Leo Mathew
  • Patent number: 7814300
    Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Jeffrey W. Scott
  • Patent number: 7811851
    Abstract: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ramachandran Muralidhar, Tushar P. Merchant, Rajesh A. Rao