Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.

Abstract: Techniques have been developed to facilitate evaluation of match and hash rule entries in ways that allow an implementation to decouple (i) the order in which match rules are applied to a first subset of packet header fields from (ii) the ordering of a second subset of packet header fields over which a non-commutative hash is computed. In short, the set and ordering of fields evaluated in accordance with a precedence order of rules need not correspond to the set or ordering of fields over which a hash is computed in a communications controller.

Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).

Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Abstract: A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

Abstract: A multi-user multiple input, multiple output (MIMO) downlink beamforming system (200) is provided to enable transmit beamforming vectors to be efficiently provided to a subset of user equipment devices (201.i), where spatial separation or zero-forcing transmit beamformers (wi) are computed at the base station (210) and used to generate precoded reference signals (216). The precoded reference signals (216) are fed forward to the user equipment devices (201.i) which apply one or more hypothesis tests (207.i, 208.i) to the precoded reference signals to extract the precoding matrix (W), including the specific transmit beamforming vector (wUE) designed for the user equipment, and this extracted information is used to generate receive beamformers (vi).

Abstract: A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.

Abstract: A vector permutation system (100) for a single-instruction multiple-data microprocessor has a set of vector registers (110) which feed vectors to permutation logic (120) and then to a negate block (130) where they are permuted and selectively negated according to control parameters received from a selected one of a set of control registers (140). A control arrangement (145, 150) selects which control register is to provide the control parameters. In this way no separate permutation instructions are necessary or need to be executed, and no permutation parameters need to be stored in the vector registers (10). This leads to higher performance, a smaller vector registers file and hence a smaller size of the microprocessor and better program code density.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract: A system (100) for reconfiguring a remote device (102) (e.g., a client device) that includes at least one processor (200) and reconfigurable logic (202) that is operatively coupled to the processor (200), employs for example, a network element that serves as a remote profile server (104) for the remote device (102). The remote device (102) includes an application profiler (206) that produces application runtime profile statistic information (120) during runtime of an application running on at least one processor (200) of the device. The remote profile server (104) includes a profile analyzer (130) that analyzes the received application runtime profile statistic information (120) to determine suitable reconfigurable logic configuration information (122) and corresponding application patch information (124) for the remote device (102).

Abstract: A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

Abstract: Power supply apparatus with overload protection comprising a switch responsive to an input signal for switching between an ON-state for supplying current from a source of power to a load and an OFF-state for interrupting the supply of current to the load, and protection means responsive to an overload condition to switch the switch to the OFF-state. The protection means is responsive to a first overload condition during an initial phase after the switch switches to the ON-state so as to switch the switch back to the OFF-state and maintain the switch in the OFF-state. The protection means is subsequently responsive to a second overload condition if the first overload condition is not detected during the initial phase so as to switch the switch to the OFF-state and subsequently switch the switch back to the ON-state after an interval of time.

Abstract: A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.

Abstract: A method of adaptive predistortion of a power amplifier, characterised in that the method comprises the steps of: storing values of a plurality of corresponding first and second coefficients; selecting one of the stored first coefficients; processing a first signal with the first coefficient to produce an input signal for the power amplifier; amplifying the input signal in the power amplifier to produce an output signal; calculating an error value from the output signal and a previously selected first coefficient; selecting a stored second coefficient corresponding with the previously selected first coefficient; updating the previously selected first coefficient with a value calculated from the error value and the second coefficient; updating the second coefficient; and replacing the previously selected first coefficient and corresponding second coefficient with the updated first and second coefficients respectively.

Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.

Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.

Abstract: Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71?). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer.

Abstract: An amplifier circuit comprises differential amplification circuitry comprising an input stage having first and second differential inputs, and an output stage, having respective first and second amplifier components with first and second differential outputs. The first amplifier component of the output stage comprises a first power transistor operably coupled to the first differential output and driven by a first differential output of the input stage, and a third power transistor operably coupled to the first differential output of the amplifier circuit and driven by a second output of the input stage. The second amplifier component comprises a second power transistor operably coupled to the second differential output and driven by a second output of the input stage, and a fourth power transistor operably coupled to the second differential output and driven by the first output of the input stage.