Abstract: A transducer (20) includes sensors (28, 30) that are bonded to form a vertically integrated configuration. The sensor (28) includes a proof mass (32) movably coupled to and spaced apart from a surface (34) of a substrate (36). The sensor (30) includes a proof mass (58) movably coupled to and spaced apart from a surface (60) of a substrate (56). The substrates (36, 56) are coupled with the surface (60) of substrate (56) facing the surface (34) of substrate (36). Thus, the proof mass (58) faces the proof mass (32). The sensors (28, 30) are fabricated separately and can be formed utilizing differing micromachining techniques. The sensors (28, 30) are subsequently coupled (90) utilizing a wafer bonding technique to form the transducer (20). Embodiments of the transducer (20) may include sensing along one, two, or three orthogonal axes and may be adapted to detect movement at different acceleration sensing ranges.

Abstract: An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells including a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line, and a second current electrode connected to the programmable fuse. The select transistor further has a semiconductor body adjacent to which the first current electrode and the second current electrode are located. These electrodes are separated by a channel. A signal terminal that is connected to the semiconductor body receives an input signal to forward bias the channel to the first current electrode during programming of the programmable fuse to increase a programming current of the programmable fuse.

Abstract: A method is described for manufacturing electronic assemblies (52). Electronic die (36) held in a plastic matrix (43) form a partially completed panel (35) of electronic assemblies (52). The panel (35) is adhesively mounted to a ceramic carrier (20) having multiple holes (22) there through. Conductive interconnects (38-1, 38-2, etc.) and other layers are applied to the panel, coupled to electrical contacts on the die (36) and external electrical contacts (39-1) for the panel (50). The panel (50) and the carrier (20) are separated and the panel singulated to release the finished electronic assemblies (52). Silicone is a preferred adhesive (27) and is dissolved using a non-polar solvent (70) that penetrates through the holes (22) in the carrier (20) to the adhesive (27). The adhesive (27) is preferentially applied using a transfer adhesive sandwich (24), that is, an adhesive layer (27) with removable plastic sheets (25, 26) on either side that can be peeled away from the adhesive (27).

Abstract: A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.

Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Abstract: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100, 100?) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110). The emitter contact (154) has a portion (154?) that overhangs a portion (1293, 293?) of the extrinsic base contact (129), thereby forming a cave-like cavity (181, 181?) between the overhanging portion (154?) of the emitter contact (154) and the underlying regions (1293, 1293?) of the extrinsic base contact (129). When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity (181, 181?) so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact (154?) closer to the base (161, 163) itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable material or springs is applied to the strip assembly in regions of the strip. The regions are located at one of a group of locations consisting of along unit edges and centered between unit edges. Heat of sufficient temperature is applied for a sufficient duration to cure the encapsulant. The step of applying pressure continues during the application of heat for curing.

Abstract: Embodiments of wireless devices and transmitters are provided, which perform embodiments of automatic gain control methods. The embodiments of wireless devices and transmitters include a ramp generator, a digital gain signal generator, a combiner, and a variable gain amplifier. The ramp generator is adapted to receive a gain control input signal and to generate a gain ramp signal based on the gain control input signal. The digital gain signal generator is adapted to generate and incorporate a gain arc into a digital gain signal. A combiner is adapted to receive and combine a digital input signal with the digital gain signal, to generate a pre-compensated digital signal. The variable gain amplifier is adapted to apply gains indicated in the gain ramp signal to a pre-adjusted analog signal, which is generated based on the pre-compensated digital signal, in order to generate a gain-adjusted analog signal.

Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).

Abstract: According to an exemplary embodiment, a method includes the step (910) of driving a buck section of a DC/DC converter with a buck signal that has a buck duty cycle and concurrently with driving the buck section, driving a boost section of the DC/DC converter with a boost signal that has a boost duty cycle, a difference existing between the buck duty cycle and the boost duty cycle. The method also includes the step (920) of monitoring an input voltage that is coupled to the buck section for a change in the input voltage, and in response to a change in the input voltage, the step (930) of changing the buck duty cycle and the boost duty cycle such that the difference between the buck duty cycle and the boost duty cycle is substantially constant.

Abstract: Integrated circuit having a Microcontroller Unit and Methods of Operation therefore. An integrated circuit comprises a microcontroller unit with synchronous logic operably coupled to non-clocked intelligent logic. The non-clocked intelligent logic is arranged to autonomously monitor multiple events associated with an operation of the synchronous logic and, in response thereto, the non-clocked intelligent logic initiates autonomously an alternate operational mode of the microcontroller unit. A method of operating a microcontroller unit is also described.

Abstract: A power management arrangement for a mobile device comprising a digital circuit block and an analog circuit block, the power management arrangement being arranged to supply a first voltage to the analog circuit and a second voltage to the digital circuit, the power management arrangement comprising: an input unit adapted to receive input voltages from a plurality of power sources; a first voltage regulator coupled to the input unit and for supplying the first voltage; a second voltage regulator for supplying the second voltage and arranged to be selectively coupled to one of the first voltage regulator and input unit; and control logic adapted to select which of the received input voltages from the plurality of power sources provides power to the first and second voltage regulators, and to determine the magnitude of the first and second voltages supplied by the first and second voltage regulators.

Abstract: A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.

Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.

Abstract: A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.

Abstract: Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value. By continuously changing the relative delay between the first driver path and the second driver path, the DCT can be driven to an optimum value.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A method for switching between instruction contexts within a time interval in a multi-mode wireless broadband processing system. The method can include executing critical task operations that complete execution within a time interval, a critical task including a plurality of critical task operations, executing non-critical task operations that are able to cross a time interval boundary, a non-critical task including a plurality of non-critical task operations, and entering a sleep mode in which no critical task operations or non-critical task operations are executed, if the critical task operations and the non-critical task operations begun in the time interval have been completed before a following time interval begins.