Abstract: A stereo decoder includes a first digital filter for producing a first filtered composite audio signal and a second digital filter for producing a second filtered composite audio signal. A sum/difference network produces a left channel signal and a right channel signal. A processor executes operational instructions that calculate a first corner frequency of a first digital filter based on a signal quality of the FM signal, calculate a first set of filter coefficients for the first digital filter based on the first corner frequency and an approximation of a filter transform, calculate a second corner frequency of a second digital filter based on the signal quality, and calculate a second set of filter coefficients for the second digital filter, based on the second corner frequency and the approximation of the filter transform.

Abstract: A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

Abstract: A device (101) for controlling the treatment of a substrate (102) with a plasma (103) is provided which comprises (a) a plasma chamber (104) adapted to generate a plasma (103); (b) a sensor (113) equipped with first (115) and second (117) electrodes that are exposed to the plasma generated within the chamber, said sensor being adapted to (i) apply a first low frequency voltage V1 to the first electrode, (ii) apply a plurality of high frequency voltages V2 . . . Vn to the first electrode, where n?2, and (iii) measure the respective currents I1 . . . In flowing through the second electrode during application of each of the voltages V1 . . . Vn, respectively; and (c) a data processing device (121) adapted to determine the densities of a plurality of ion species based on currents I1 . . . In and on a mathematical model or on calibration data relating to the plasma chamber.

Abstract: A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.

Abstract: A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract: A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon.

Abstract: Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Abstract: A method of communicating between a mobile communication device including a power supply, and a base station. The mobile device has first and second alternative communication modes, the first communication mode having higher quality of service and higher power consumption than the second communication mode. The second communication mode is adopted in response to a characteristic of the mobile device power supply indicative of a reduced reserve of power in the power supply, and a state indication is transmitted from the mobile device to the base station. The base station can respond to the state indication from the mobile device by modifying a communication characteristic of the base station with the mobile device, whereby to tend to compensate for the mobile device switching between the first and second communication modes.

Abstract: A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.

Abstract: Techniques have been developed to facilitate concurrent evaluation of hash rule entries in ways that allow an implementation to maintain a deterministic resultant hash irrespective of variations in the allocation of particular rules to particular storage banks or evaluation logic, such as may occur with rule set revisions. Similarly, uniform deterministic hash results can be assured even across a range of implementations that support greater or lesser levels of concurrent rule evaluations.

Abstract: A three-axis MEMS transducer featuring a caddie-corner proof mass comprises a planar main body portion of conductive material and a planar extra mass caddie-corner feature. The main body portion includes a width, length, and at least four side edges. An x-axis sense direction is defined from a first side edge to an opposite first side edge and a y-axis sense direction is defined from a second side edge to an opposite second side edge. The x-axis sense direction is perpendicular to the y-axis sense direction. The main body portion further includes at least two corners. The caddie-corner feature is positioned about at least one of the two corners of the main body portion. The caddie-corner feature and the main body portion comprise a single proof mass having a z-sense pivot axis disposed at an angle of ninety degrees to a diagonal extending from the caddie-corner feature to an opposite corner of the main body portion.

Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract: A power supply circuit that accurately generates output voltages with the same regulator includes a regulator for generating a first output voltage from an input voltage. A first switch circuit, connected to the regulator, selectively outputs the first output voltage of the regulator as a second output voltage from the power supply circuit. A pre-charge circuit, connected to the regulator and the first switch circuit, generates the second output voltage from the input voltage before the first output voltage of the regulator is output as the second output voltage while controlling the first switch circuit.

Abstract: The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balancing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.

Abstract: A radio receiver for receiving a signal is provided. The radio receiver comprises an equalizer configured to perform a constant modulus algorithm initialized using a first set of coefficients on the received signal and for generating an equalized signal. The radio receiver further comprises a demodulator coupled to the equalizer for demodulating the equalized signal. The radio receiver further comprises a lowpass filter coupled to the demodulator for lowpass filtering the demodulated signal to detect a spurious signal and to generate an offset signal. The radio receiver further comprises a coefficient generator coupled to the lowpass filter and configured to compare the offset signal to a predetermined threshold, and if the offset signal satisfies a predetermined condition in relation to the predetermined threshold, then to generate a second set of coefficients for re-initializing the constant modulus algorithm.

Abstract: A method (700) and apparatus (600) are described for performing parallel decoding in connection with 2M-1 parallel ACS unit in ACS unit (110), track buffer (112) and voting unit (114) in an Ultrawide Bandwidth (UWB) receiver having a parallel trellis decoder for decoding a message sequence encoded according to a convolutional code. Outputs from the track buffer can be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.