Abstract: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Abstract: A voltage multiplier (10) including a first clocked multiplier stage (12) having an input and an output and a second clocked multiplier stage (14, 16) having an input and an output is provided. The voltage multiplier further includes an input level regulator (18) coupled to the input of the first multiplier stage. The voltage multiplier further includes a feedback bias control circuit (32) coupled to the input level regulator, wherein the feedback bias control circuit is further coupled to receive the output (50) of the second multiplier stage, and wherein the feedback bias control circuit generates a feedback signal (58) affecting an output of the input level regulator based on a comparison between a voltage proportional to a voltage at the output of the second clocked multiplier stage and a reference voltage.

Abstract: A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the exposed surface in covered areas of the one or more layers to be patterned and does not cover the exposed surface in bared areas of the one or more layers to be patterned. One or more recesses are formed in the layers to be patterned by at least partially removing the layers to be patterned in the bared areas. The hard-mask layer is ten removed. After removing the hard-mask layer the recess is filled with a filling material.

Abstract: A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).

Abstract: A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.

Abstract: A method for scheduling a processing of packet stream channels comprises: determining whether at least one packet stream channel comprises a frame ready for processing; if at least one packet stream channel comprises a frame ready for processing, identifying a frame ready for processing having a highest priority; and scheduling the identified highest priority frame for processing. The method further comprises prioritising frames ready for processing based on at least one of: a frame availability time and an estimated processing time, for each frame.

Abstract: A method of manufacturing a semiconductor device on a substrate. The method may include forming a non-volatile memory in a memory area of the substrate. The forming non-volatile memory on a substrate may include formation in the memory area of a floating gate structure and of a control gate structure which is in a stacked configuration with the floating gate structure. One or more gate material layer may be formed in a logic area of the substrate. After forming the control gate structure and the gate material layer, a filling material layer may be deposited over the logic area and the memory area. The filling material layer may be partially removed by reducing the thickness of the filling material in the logic area and the memory area, at least until a top surface of the one or more gate material layer is exposed. Logic devices may be formed in the logic area, the formation may include forming a logic gate structure from the gate material layer.

Abstract: An accelerometer (50, 100, 120, 130) includes a substrate (58) and a proof mass (54) spaced apart from a surface (56) of the substrate (58). Compliant members (62) are coupled to the proof mass (54) and enable the proof mass (54) to move parallel to the surface (56) of the substrate (58) in a sense direction (68). Proof mass anchors (60) interconnect the compliant members (62) with the surface (56). The accelerometer (50, 100, 120, 130) includes an over-travel stop structure (52, 102, 122, 132) having stop anchors (70, 72) coupled to the substrate (58). The stop anchors (70, 72) are coupled to the substrate (58) at positions (76) on the surface (56) residing at least partially within an anchor attach area (71) bounded in the sense direction (68) by locations (78) of the proof mass anchors (60) on the surface (56).

Abstract: Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor.

Abstract: A method and device for sharing data. The method include: receiving by a direct memory access controller, a data read instruction; wherein the read data instruction can be a shared data read instruction or a non-shared data read instruction; determining whether to fetch a requested data block from a first memory unit to a second memory unit by applying a direct memory address control operation; wherein the second memory unit is accessible by a processor that generated the shared data read instruction; fetching the requested data block from the first memory unit to the second memory unit by applying a direct memory access control operation, if the read data instruction is a non-shared data instruction or if the read data instruction is a shared data instruction but the requested data is not stored in the second memory unit; and retrieving a requested data block from a second memory unit.

Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill.

Abstract: Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

Abstract: An integrated circuit is configured to be in a calibration mode of operation to establish a desired output impedance of a driver circuit. A predetermined constant voltage is established at a circuit node within the integrated circuit. A calibration current is conducted through a transistor connected in series with a variable value resistance in the integrated circuit at the circuit node. A resistance value of the variable value resistance is varied to establish a value of the calibration current which establishes the desired output impedance. The calibration mode is exited and a functional mode is entered. A calibrated resistance value is used during the functional mode of operation. The calibration current is conducted as a calibrated current through the transistor and calibrated resistance value. Variation of the calibrated current is corrected in response to voltage and process variations to maintain the calibrated current and output impedance of the driver circuit.

Abstract: A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch and the data node. The coupling circuit is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit. The power down control circuit is for disabling the first latch during the power down mode and for a time period after a transition from the power down mode to the normal operation. This allows the second latch to set the state of the first latch when transitioning from the power down mode to the normal mode. Thus normal operation can be fast, and the power down mode can have low leakage current.

Abstract: A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities.

Abstract: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial growth of an epitaxial semiconductor layer (96).

Abstract: A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set of input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit.

Abstract: A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.