Abstract: A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.

Abstract: According to one aspect of the present invention, an electronic assembly is provided. The electronic assembly comprises a substrate with a lead connected thereto and first and second microelectronic components on the substrate. The first microelectronic component has first and second portions. A plurality of conductors interconnects the first microelectronic component and a selected one of the lead and the second microelectronic component. A first of the conductors contacts the first portion of the first microelectronic component and has a first inductance, and a second of the conductors contacts the second portion of the microelectronic component and has a second inductance. The second inductance is greater than the first inductance.

Abstract: A method that includes defining a transmission schedule of a TDM data frame that includes multiple TDM time slots allocated for transmitting data over a TDM line; the method is characterized by including: providing a transmission clock signal having a transmission clock frequency to the TDM line, providing a first clock signal having a first clock frequency to data sources that belong to a first group of data sources and providing a second clock signal having a second clock frequency to data sources that belong to a second group of data sources; wherein the first clock frequency and the second clock frequency are higher than the transmission clock frequency; pre-fetching, to a first intermediate storage a data segment from a data source out of the first group of data sources in response to a fullness level of the first intermediate storage unit and to the transmission schedule; pre-fetching, to a second intermediate storage a data segment from a data source out of the second group of data sources in response

Abstract: A method is provided for transmitting data from a transmitting device (121) to a receiving device (125). The transmitting device transmits a first data frame (200) to a receiving device a first time (3100). Then it consecutively transmits the first data frame to the receiving device second through Nth times (3101-310N), each of second through Nth first data frame transmissions being made a first predetermined time period (350) after a respective previous first data frame transmission. After this, the transmitting device transmits a second data frame (200) to the receiving device a second predetermined time period (360) after the Nth first data frame transmission. In this method, N is an integer greater than 1, and the second predetermined time period is less than the first predetermined time period.

Abstract: A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produce a result vector having the number of vector elements. Each vector element of the result vector is associated with an arithmetic logic cell that has a first input that can receive any vector element from the first vector and a second input that can receive any vector element from the second vector. Accordingly each vector element of the result vector is a function of any two individual vector elements of the operand vectors. By applying the operand vector elements to the appropriate arithmetic logic cells, and by selecting the appropriate arithmetic operation, complex vector operations can be performed efficiently.

Abstract: A system that includes a phase locked loop and an activation circuit; wherein the phase locked loop includes an oscillator, a frequency divider, a phase detector, a control circuit, and a memory circuit. The activation circuit is adapted to activate the memory circuit and the oscillator; to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods. The timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.

Abstract: A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit.

Abstract: A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

Abstract: In the field of step-down voltage conversion, it is known to regulate an output of a DC-DC converter circuit with both a Pulse Wave Modulation voltage signal or a Pulse Frequency Modulation voltage signal, depending upon a current demand made upon the DC-DC converter circuit. Typically, circuits to generate both voltage signals are provided and selection of the appropriate regulation mode is achieved by means of a pin and decision software controlling the pin. However, the use of the pin and the software is an overhead that is desirably avoided. Consequently, the present invention provides a voltage conversion apparatus comprising a signal analyzer to analyze a load current signal and compare a characteristic of the load current signal to at least one predetermined criterion. Regulation by the PWM signal or the PFM signal is selected in response to the evaluation of the comparison with the at least one criterion.

Abstract: A series regulator circuit for reducing current consumption, enabling switching between different current consumption modes, and suppressing output voltage fluctuations. A constant current source 20, connected to an input voltage line, is connected to a ground voltage line via a resistor element 21 and transistor B1. Gate terminals of transistors M2, M4 are connected between the constant current source 20 and transistor B1. The transistor M2 is connected to the input voltage line via a transistor M1 activated in a high current mode. The source terminals of the transistors M2, M4 function as the series regulator circuit output terminal, which is connected to the ground voltage line via a resistor element 23 and transistor M3, activated in a high current mode, or via resistor elements 24, 25. A connection node between the resistor elements 24, 25 is connected to a base voltage of the transistor B1.

Abstract: A MEMS capacitive device (90) includes a fixed capacitor plate (104) formed on a surface (102) of a substrate (100). A movable capacitor plate (114) is suspended above the fixed capacitor plate (104) by compliant members (116) anchored to the surface (102). A movable element (120) is positioned in spaced apart relationship from the movable capacitor plate (104) and has an actuator (130) formed thereon. Actuation of the actuator (130) causes abutment of a portion of the movable element (120) against a contact surface (136) of the movable plate (114). The abutment moves the movable plate (114) toward the fixed plate (104) to alter a capacitance (112) between the plates (104, 114). Another substrate (118) may be coupled to the substrate (100) such that a surface (126) of the substrate (118) faces the surface (102) of the substrate (100). The movable element (120) may be formed on the surface (126).

Abstract: A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit.

Abstract: An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.

Abstract: An ultra wideband direct sequence code division multiple access (UWB DS-CDMA) (101) transmitter is provided. It includes a first multiplier (125) receiving two input signals, where the input signals are selected from a multi-level code signal (117), a transmit data signal (123), and a radio frequency (RF) center frequency signal (121), and responsive to the two input signals, generating a combined signal (127). Further included is a network (119) receiving a code-clock signal (113) aligned with the multi-level signal (117), multiplying the frequency of the code-clock signal (113) by a factor, and responsive thereto, producing the RF center frequency signal (121). Also provided is a second multiplier (129) receiving the combined signal (127) and the other of the input signals (117, 123, 121), and responsive thereto, generating an output signal (131).

Abstract: A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.

Abstract: An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.

Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).

Abstract: A method of communication comprising sending communication signals switched between dominant and recessive values at clock intervals in frames over a serial data bus from at least one of a plurality of sending nodes to a plurality of receiving nodes. The receiving nodes have an operational state and a standby state in which the current consumption of the node is reduced compared to the operational state. The receiving nodes include wake-up trigger means for triggering transition from the standby state to the operational state in response to the communication signals.

Abstract: A cell phone device having a camera, an imaging unit and a display unit, which are joined with each other. The imaging unit and the display unit may be separated and used in a separated state. A display housing includes the display unit, a speaker, and a microphone. A keypad housing includes the imaging unit. The display housing and the keypad housing each include a local communication IF unit for performing wireless communication and a battery for supplying power to each function block. When the display housing and the keypad housing are separated, the image generated by the imaging unit is output to the display unit via the local communication IF units. A recording instruction is then generated by operating the display housing while checking the image on the display unit.