Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A transducer package 20 includes a substrate 32 having a first axis of symmetry 36 and a second axis of symmetry 38 arranged orthogonal to the first axis of symmetry 36. At least a first sensor 50 and a second sensor 52 each of which are symmetrically arranged on the substrate 32 relative to one of the first and second axes of symmetry 36 and 38.The first and second sensors 50 and 52 are adapted to detect movement parallel to the other of the first and second axes of symmetry 36 and 38. The first sensor 50 is adapted to detect movement over a first sensing range and the second sensor 52 is adapted to detect movement over a second sensing range, the second sensing range differing from the first sensing range.

Abstract: A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.

Abstract: A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N2/D2), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.

Abstract: An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.

Abstract: Local Interconnect Network message budget calculation error is reduced by utilizing an eight bit time measurement of the sync byte in the message header. The method determines the header budget separately from the data budget, simplifying the required logic. The sync byte reference time is multiplied by the message data size to determine the data budget.

Abstract: A technique of operating a communication device includes identifying a signal null associated with a signal to be transmitted on a first communication channel. A channel gain of the first communication channel is adjusted at a time that substantially coincides with the signal null to reduce transient noise spectrum coupled from the first communication channel to one or more second communication channels.

Abstract: A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

Abstract: A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed ends of the N regions (32, 52, 103) are terminated by N+ layers (31, 51, 131). Silicide layers (24, 34, 44, 54, 134, 124) are provided in contact with both ends of the parallel N and P regions (22, 32, 42, 52, 100, 103), thereby forming at the first end ohmic contacts (28, 48) with the P+ regions (21, 41, 121) and Schottky contacts (37, 57) with the N regions 32, 52, 103) and at the second, opposite end, ohmic contacts (38, 58) with the N+ regions (31, 51, 131) and Schottky contacts (27, 47) with the P regions (22, 42, 100). When forward biased current flows in both N (32, 52) and P (22, 42) regions thereby reducing the forward drop.

Abstract: A system (50) includes a material layer (52) having an opening (62) extending through it and a pumping device (54) positioned behind the layer (52). A target element (56) is positioned in front of the material layer (52). In a partial cooling mode (124), the pumping device (54) drives a jet (134) of coolant through the opening (62) toward the target (56). Transducers (58, 60), positioned at opposing ends of the opening (62), produce output signals (130, 132) that perturb the jet (134) to partially control its oscillation. The jet (134) spreads from a location (96) on the target element (56) in one direction (142) to provide uniform cooling over a portion (126) of the target element (56) in the direction (142), and the jet (134) non-uniformly spreads in another direction (144) to provide non-uniform cooling over a portion (128) of the target element (56) in the other direction (144).

Abstract: A wireless transmitter is configured to map N first samples of a first discrete Fourier transform (DFT) of a group of coded symbols to M sub-carriers according to a first sub-carrier mapping rule. In this case, M is greater than N. The wireless transmitter is also configure to perform a first inverse DFT (IDFT) on the M sub-carriers to provide M second samples and clip the M second samples according to a clipping rule to provide M third samples. The wireless transmitter is further configured to perform a second DFT on the M third samples, de-map the M third samples to N fourth samples, and map the N fourth samples to O subcarriers according to a predetermined second subcarrier mapping rule. In this case, O is greater than or equal to M.

Abstract: A drive arrangement for activating a car safety device activation element, such as an air bag, comprises a drive circuit, which is coupled to the car safety device activation element. The drive circuit generates an activation signal which activates the car safety device. The arrangement includes a power supply transistor which is coupled in series with a power supply input of the drive circuit and an energy reservoir such as a capacitor. The arrangement further comprises control means which controls the supply voltage to the drive circuit by controlling the power supply transistor to operate in an active region to provide a voltage drop during activation of the car safety device activation element. Hence, a significant voltage drop and thus energy dissipation may be moved from the drive circuit to the power supply transistor. The drive circuit may therefore be reduced in size and the power supply transistor may be implemented in a cheap technology suitable for energy dissipation.

Abstract: First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.

Abstract: Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.

Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

Abstract: A circuit includes a variable frequency generator circuit and a quantization circuit. The variable frequency generator circuit provides a discontinuous switching frequency signal. The variable frequency generator circuit varies the discontinuous switching frequency signal between a first and second frequency while avoiding at least one frequency band between the first and second frequency. The quantization circuit provides a plurality discrete switching signals each separated by a second frequency band that vary in accordance with the discontinuous switching frequency signal, wherein the avoided frequency band of the discontinuous switching frequency signal is greater than the second frequency band.

Abstract: A test apparatus and device under test has a probe that can be located very close to contact pads and that requires very few solder connections. In addition, the probe can be configured to meet any appropriate and desired electrical specification while still using a same circuit board. There is no need to attach discrete components to a circuit board. Thus, by using a configurable probe, a single circuit board may be used with multiple probes or a reconfigurable probe to test for compliance with a variety of different electrical specifications having different requirements.

Abstract: A microprocessor may include a logic circuit for executing instructions of a data processing application. The microprocessor may have a timer system which includes a clock counter connected to a clock input for receiving a clock signal and counting a number of cycles of the clock signal. A clock comparator may be connected the clock counter and to a timer register in which a timer reference value can be stored. The clock comparator may compare a number of cycles of the clock signal with the timer reference value and generate a timer signal based on the comparison. The timer system may have a timer output for outputting timer signal. The timer system may include a control input for receiving a digital value representing a measured value of a sensed parameter of a device and a control register in which a control reference value can be stored. A control comparator may be connected the control input.

Abstract: A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits.

Abstract: A method of decoding in a wireless receiver, a wireless transmission from a predefined user, the method comprising: receiving a wireless transmission signal (r(m)); determining a one or more interfering spreading codes (si(m)) contributing to the received wireless transmission signal (r(m)); estimating a one or more interferer symbols ({circumflex over (b)}i(m)) from the received wireless transmission signal (r(m)) and the or each interfering spreading codes (si(m)); calculating a one or more scaling factors (Pi(m)) at which the or each of the interferer symbols ({circumflex over (b)}i(m)) was originally transmitted; simulating an interference signal i(m) in the received wireless transmission signal (r(m)); removing the simulated interference signal i(m) from the received wireless transmission signal (r(m)) to produce a processed wireless signal (o(m)); and estimating a one or more symbols {circumflex over (b)}(m) transmitted by the predefined user in the processed wireless signal (o(m)).