Abstract: Amplifier apparatus comprising a power amplifier having an operating frequency in the radio frequency or microwave or higher ranges and a pre-distorter, the characteristics of the power amplifier comprising a distortion from a linear transfer function. The pre-distorter comprises a non-linear path and a linear path including amplifiers having substantially identical physical characteristics, an input divider responsive to an amplifier input signal for applying respective pre-distorter input signals to the paths, and an output coupler for combining the signals from the linear path and the non-linear path to produce a pre-distorted signal. The characteristics of the pre-distorter comprise a distortion relative to a linear transfer function that compensates for the distortion of the transfer function of the power amplifier.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device.

Abstract: A locking mechanism of an inertia reel assembly of a vehicular seatbelt restraint system is selectively disabled based on a latch status of a seatbelt buckle of the seatbelt restraint system. In one embodiment, a sensor at a latch assembly determines whether the seatbelt buckle is engaged with the latch assembly and provides an output signal based on this determination. A controller receives the output signal and selectively drives an actuator based on the output signal so as to enable or disable the locking mechanism of the inertia reel assembly. By disabling the locking mechanism of the inertia reel assembly when the seatbelt buckle is detected as unlatched, an occupant is able to quickly latch the seatbelt buckle even in the event of an inertial event that otherwise would have prevented any further extension of the seatbelt.

Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Abstract: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The through hole heat spreader pins (71) may be formed as an integral part of the exposed pad (52) or may be solidly connected with the exposed pad (62).

Abstract: A rate control system for a video encoder including rate control logic which determines a first QP corresponding to a selected encoding layer of multiple encoding layers, and scaling logic configured to scale the first QP to a second QP corresponding to any other encoding layer based on at least one encoding layer parameter. A template of stored QP values may be used to reduce computational complexity, such as a QP value for each frame interval or a QP value for each of multiple rate control interval complexity values. The QP values in the template may be predetermined or programmed and updated during periodic training sessions. Several encoding layer parameters are contemplated, such as any combination of bit rate, frame rate and frame resolution. The scaling logic may be configured to scale from any one encoding layer to another and vice-versa for bi-directional scaling.

Abstract: A method for decoding an input bit stream encoded using Huffman encoding generates a lookup table using a standard Huffman code book. Thereafter, at least three bits are extracted from the input bit stream. The at least three bits extracted are used to traverse the lookup table. Subsequently, a data set corresponding to a Huffman code word is accessed, thereby decoding the input bit stream.

Abstract: A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.

Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).

Abstract: A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.

Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, forming a main mask over the dielectric layer, the main mask comprising a plurality of main mask openings arranged in a regular pattern extending over the dielectric layer, using a selector mask to select some of the plurality of main mask openings and removing portions of the dielectric layer through the selected some of the plurality of main mask openings to provide openings extending through the dielectric layer to the layer.

Abstract: A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.

Abstract: A technique for extracting a control channel from a received signal includes storing interleaved control channel elements of the received signal in a control channel region of a memory. First addresses for first elements that are included in a first control channel are then generated using a first circuit. Finally, the respective first elements are read, using a second circuit, from the control channel region of the memory according to the generated first addresses to provide the first control channel in a deinterleaved form.

Abstract: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.

Abstract: A method (1300) is provided for generating one or more waveforms (130, 140). The method includes: generating a first toggle signal (1130, 1330) in response to a clock signal (1110), the first toggle signal having one of a first positive shape, a null shape, and a first negative shape for each cycle of the clock signal; multiplying the first toggle signal by a first coefficient signal to create a first intermediate signal (1440); generating a second toggle signal (1140, 1330) in response to the clock signal, the second toggle signal having one of a second positive shape, the null shape, and a second negative shape for each cycle of the clock signal; multiplying the second toggle signal by a second coefficient signal to create a second intermediate signal (1440); and generating a first output signal (1170) by adding the first intermediate signal and the second intermediate signal together (1350).

Abstract: A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.

Abstract: A hetero-structure field effect transistor (HFET). The HFET may include a first contact and a second contact and a hetero-junction structure. The hetero-junction structure may include a first layer made from a first semiconductor material and a second layer made from a second semiconductor material. An interface at which the first layer and the second layer are in contact with each other may be provided, along which a two dimensional electron gas (2DEG) is formed in a part of the first layer directly adjacent to the interface, for propagating of electrical signals from the first contact to the second contact or vice versa. The transistor may further include a gate structure for controlling a conductance of the channel; a substrate layer made from a substrate semiconductor material, and a dielectric layer separating the first layer from the substrate layer. The second contact may include an electrical connection between the substrate layer and the first layer.

Abstract: A package for enclosing volatile corrosion inhibiting materials includes a first enclosure barrier being fabricated from one or more gas-impermeable materials and defining a first enclosed space. The package further includes a substrate having one or more volatile corrosion inhibitor materials disposed thereon, with the substrate being disposed within the first enclosed space. In some embodiments, a second enclosure barrier being fabricated from a gas-permeable, solid particle-impermeable material is disposed in the first enclosed space, and defines a second enclosed space inside of the first enclosed space. In such embodiments, the substrate is preferably disposed within the second enclosed space.

Abstract: A semiconductor process and apparatus includes forming PMOS transistors (90) with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer (91, 136) on or adjacent to sidewalls of the PMOS gate structure as either a hydrogen-rich implant sidewall spacer (91) or as a post-silicide hydrogen-rich implant sidewall spacer (136), where the hydrogen-rich dielectric layer acts as a hydrogen source for passivating channel surface defectivity under the PMOS gate structure.