Abstract: A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Abstract: The present application relates to an orthogonal frequency division multiplexing (OFDM) receiver and a method of operating the receiver for performing a cell search. A coarse correlator block is provided to detect one cell out of a by plurality of wireless communication cells by determining first correlation metric values by applying a partial correlation comprising part-wise correlating sample data with each one of a first set of phase-rotated reference sequences and non-coherent combining. The maximum of the first correlation values yields to a cell identifier value. A fine correlator block is provided to estimate a fine time offset value for the one wireless communication cell by determining second correlation values by applying a correlation comprising correlating the he sample data with each one of a second set of phase-rotated reference sequences. The maximum of the second correlation values value yields to a fine time offset.

Abstract: A method and apparatus are provided for classifying received network frames (234) by extracting frame header data (e.g., n-tuple) which is combined with a key insert value (e.g., embedded prefix value “OP01, OP02, . . . OP0OP1”) to generate a lookup key (217), where the key insert value is generated by decoding a key composition rule (212) to extract a constant value (OP0) and a repeat value (OP1), and then replicating the constant value one or more times specified by the repeat value.

Abstract: Apparatus are provided for amplifier systems and related integrated circuits are provided. An exemplary integrated circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the integrated circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the integrated circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.

Abstract: Apparatus, systems, and fabrication methods are provided for sensing devices. An exemplary sensing device includes a first sensing arrangement to measure a first property and provide one or more measured values for the first property, a second sensing arrangement to measure a second property, a storage element coupled to the second sensing arrangement to maintain a stored value for the second property measured by the second sensing arrangement, and a control system coupled to the first sensing arrangement and the storage element to determine one or more calibrated measurement values for the first property using the one or more measured values for the first property from the first sensing arrangement and the stored value for the second property.

Abstract: A semiconductor die includes a device structure having a micro-electronic device located at a surface of a substrate and a cap coupled to the device structure with the micro-electronic device positioned in a cavity located between the cap and the substrate. A sacrificial material is provided within the cavity, coupling the cap to the device structure. The sacrificial material is heated in the cavity to cause the sacrificial material to decompose to a gaseous species. The presence of the gaseous species in the cavity increases a pressure level in the cavity from an initial pressure to a final pressure.

Abstract: Systems and methods for self-checking a direct memory access system are disclosed. These may include generating a check sum value associated with a first job of the plurality of jobs, the first job comprising a read job; if a first predetermined check value is available, comparing the first check sum value with the first predetermined check value; generating a second check sum value associated with a last job of the plurality of jobs, the last job comprising a write job; if a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and if the second predetermined check value is not available, comparing the first check sum value with the second check sum value.

Abstract: A processing device and a method of executing an instruction sequence are described. The processing device comprises a status register for providing a status word, wherein execution of an instruction by the processing device comprises updating the status word, wherein the instruction sequence comprises a subsequence of one or more selected instructions, and wherein execution of a selected instruction by the processing device further comprises a status check which comprises: providing a set of valid status words; verifying whether the updated status word is in the set of valid status words; and initiating an alert action if the updated status word is not in the set of valid status words.

Abstract: A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.

Abstract: A method includes, in one implementation, receiving a first set of instructions of a first thread, receiving a second set of instructions of a second thread, and allocating queues to the instructions from the first and second sets. During a time when the first and second threads are simultaneously being processed, changeable number of queues can be allocated to the first thread based on factors such as the first and/or second thread's requirements or priorities, while maintaining a minimum specified number of queues that are allocated to the first and/or second thread. When needed, one thread may be stalled so that at least the minimum number of queues remains reserved for another thread while attempting to satisfy thread-priority requests or queue-requirement requests.

Abstract: The present application describes a SoC device with observer units for monitoring a state of a respective functional unit of the SoC combiner units for generating combinational events based on one or more observer events issued by the observer units and one or more feedback events from issued by action units and action units for generating feedback events and/or action request based the on at least one combinational event.

Abstract: A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.

Abstract: An open-circuit detection system for an integrated circuit (IC) includes a wire (e.g., part of a wire mesh for device protection) and circuitry for detecting open-circuit conditions in the wire. A first signal generator (e.g., a linear-feedback shift register) applies a binary sequence to a first end of the wire. Switched resistors are connected between a second end of the wire and both a voltage supply and ground. A comparator compares the binary sequence and a signal based on the voltage at the second end of the wire to check for the open-circuit condition. Logic circuitry closes one of the first and second switches as a function of a value in the binary sequence. The comparator checks for the open-circuit condition in the wire randomly and intermittently, which reduces power consumption.

Abstract: Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.

Abstract: A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Abstract: A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.

Abstract: A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialization data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialization data.

Abstract: An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an induced signal in dependence on the radio frequency signal; a connecting line connected to a pick-off point of the coupling line for picking off the induced signal from the coupling line; and a conductive part for shielding the coupling line against electromagnetic interference and for enhancing inductive coupling between the signal line and the coupling line. The conductive part may have a uniform flat surface facing the coupling line. The signal line may extend parallel to the surface. The coupling line may extend parallel to the signal line and may be arranged between the surface and the signal line.

Abstract: A method of bonding a cap wafer to a device wafer includes heating the device wafer and the cap wafer in the chamber, cooling the device wafer and the cap wafer in the chamber, pressurizing the chamber, introducing gas into the chamber while the chamber is pressurized to accelerate a rate of one of a group consisting of the heating and the cooling, and applying pressure to the device wafer and the cap wafer while a bond is formed between the device wafer and the cap wafer.