Patents Assigned to Freescale
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Publication number: 20090313407Abstract: A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an electric synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the electric synchronisation signal, data to the central control unit. The central control unit further includes a discharge signal generator for outputting a discharge signal via the data connection to the data processing unit.Type: ApplicationFiled: August 1, 2006Publication date: December 17, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Philippe Lance, Arlette Marty-Blavier, Eric Rolland
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Publication number: 20090313414Abstract: A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.Type: ApplicationFiled: August 1, 2006Publication date: December 17, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Stephen Pickering, Edward J. Hathaway, Christian Vetterli, Michael C. Wood
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Publication number: 20090310726Abstract: A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer.Type: ApplicationFiled: August 2, 2006Publication date: December 17, 2009Applicant: Freescale Semiconductor, IncInventors: Yaron Alankry, Eran Glickman, Erez Parnes, Daniel Rozovsky
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Publication number: 20090310653Abstract: A demodulator (150) in a receiver (100) includes a correlator (240) for de-spreading a spread-spectrum signal, and decision module (250) for detecting a preamble and for synchronizing to data frames of the spread spectrum signal. The demodulator includes symbol timers (231 and 233) that allow the demodulator to correlate to two preamble symbols simultaneously, where the two preamble symbols occur one-half a symbol period apart. The correlator includes a correlator structure (301) having taps that correct for any frequency offset of a carrier signal. The correlator correlates to each of the two preamble symbols a plurality of times through oversampling, where each correlation compensates for a different amount of frequency offset. By analyzing occurrence of peaks in magnitude of the correlations, the decision module detects the preamble and selects weights for the taps to de-spread data frames received after the preamble.Type: ApplicationFiled: June 17, 2008Publication date: December 17, 2009Applicant: Freescale Semiconductor, Inc.Inventor: ROBERT MARK GORDAY
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Patent number: 7632698Abstract: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in encapsulating material (24).Type: GrantFiled: May 16, 2006Date of Patent: December 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Stephen R. Hooper, David E. Heeley
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Patent number: 7634396Abstract: In accordance with the present invention, there is provided a method for creating a Bus Functional Model of an Integrated Circuit. The method comprises the following steps: providing (102) a detailed specification of said Integrated Circuit, defining (104) an architecture for said Bus Functional Model. In the following step data contained in the detailed specification of the Integrated Circuit are mapped (106) between the specification and the predefined BFM architecture. The BFM architecture contains at least one of the following constructs: Interface Tasks (202), Internal Data Elements (204), Processes (208), Finite State Machines (210), Conditions (206), Actions (212) and Signals (214). In the following step (110) the formal description of Bus Functional Model in Formal Description Language is created.Type: GrantFiled: April 25, 2002Date of Patent: December 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Lyubov Zhivova, Sergey Korotkov, Oleg Kruzhkov, Igor Makhlushev, Alexander Nekrasov, Ivan Selin
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Patent number: 7634275Abstract: A method is provided for accommodating periodic interfering signals in a wireless network. In this method, a network scans a transmission medium to locate any interfering signals. If it finds interfering signals, the scan determines their period, and the network alters the period of its superframes such that: either the period of the superframes is equal to the period of the interfering signals; the period of the superframes is an integer multiple of the period of the interfering signals; or the period of the interfering signals is an integer multiple of the period of the superframes. The network then alters the position of the superframes relative to the position of the interfering signals to arrange things such that no portion of the interfering signal interferes with a superframe beacon, such that that a maximum amount of contiguous channel time is provided in each superframe, or both.Type: GrantFiled: July 1, 2003Date of Patent: December 15, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Knut T. Odman
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Patent number: 7633307Abstract: A method is provided for testing semiconductor devices. In accordance with the method, a first usage temperature T1 is obtained which represents the maximum or minimum temperature to which a semiconductor device will be exposed during its first use by a customer. The semiconductor device is then tested for defects while ramping the temperature to which the device is exposed from a first temperature T0 to the temperature T1.Type: GrantFiled: December 16, 2005Date of Patent: December 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Paul J. Whipple, Vincent V. Vu
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Patent number: 7634703Abstract: A decoder for a wireless communication device comprising a calculator for calculating the modulo of a linear approximation of a MAX* function; and a selector for selecting a MAX* output value from the group a(n)mod F, b(n)mod F, and the calculated modulo based upon a determination as to whether a predetermined threshold value for |a(n)?b(n)| has been met, where a(n) is a first state metric, b(n) is a second state metric, C is the predetermined threshold value and F is a value greater than |a(n)?b(n)|.Type: GrantFiled: December 3, 2004Date of Patent: December 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Gideon Kutz, Amir I. Chass
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Patent number: 7632715Abstract: A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material. A concentration of the filler material is increased in all areas laterally adjacent each of the plurality of semiconductor die.Type: GrantFiled: January 5, 2007Date of Patent: December 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee, Robert J. Wenzel
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Publication number: 20090303872Abstract: A device having under-run management capabilities and to a method for managing under-runs. The method includes providing, to a memory unit, channel information from multiple channels; allocating time slots for communication channel transmissions; the method is characterized by including: sending, during a time slot allocated for a transmission of channel information from an enabled communication channel, to the shift register channel information of an enabled communication channel, serially outputting the received channel information from the shift register towards a communication line while serially replacing the outputted channel information by a predefined content such that the shift register stores a communication channel disable code when an under-run occurs; defining a communication channel as a disabled communication channel once the under-run occurs; and transmitting, during a time slot allocated to a disabled communication channel, idle signals to the communication line.Type: ApplicationFiled: November 9, 2005Publication date: December 10, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Eran Glickman, Yaron Alankry, Adi Katz
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Publication number: 20090305739Abstract: A mobile communications device. includes a communication unit for communicating with another device. The mobile communications device further has a communication unit for communicating with another device and at least one other component. A controller is connected to the communication unit and the component. The controller can control the component, during at least a part of time the communication unit is in a communicating mode, based on an operation of the communication unit.Type: ApplicationFiled: September 25, 2006Publication date: December 10, 2009Applicant: Freescale Semiconductor , Inc.Inventors: Sylvain Gavelle, Fabrice Cotdeloup
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Publication number: 20090302364Abstract: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Applicant: Freescale Semiconductor, IncInventors: Fabio Duarte de Martin, Fabio de Lacerda, Alfredo Olmos
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Patent number: 7630272Abstract: A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.Type: GrantFiled: February 19, 2007Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Prashant U. Kenkare, Ravindraraj Ramaraju, Troy L. Cooper
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Patent number: 7630429Abstract: Known chip equalizers for Wideband-Code Division Multiple Access (W-CDMA) employ a co-efficient calculator that implements a Minimum Mean Square Error (MMSE) solution to a least squares technique for obtaining equalizer coefficients in response to receipt of a pilot sequence. However, this solution results in an undesirably high processing overhead in downlink receivers operating in a W-CDMA communications system. Consequently, the present invention provides a computationally simpler technique to calculate equalizer coefficients by implementing a minimum-norm solution to the least squares problem.Type: GrantFiled: June 8, 2005Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Arik Gubeskys, Amir Chass
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Patent number: 7629220Abstract: A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.Type: GrantFiled: June 30, 2006Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Marius Orlowski
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Patent number: 7628072Abstract: A MEMS device includes a substrate; a movable mass suspended in proximity to the substrate; and at least one suspension structure coupled to the movable mass for performing a mechanical spring function. The at least one suspension structure has portions that move in tandem when the MEMS device is subject to at least one stimulus in a sensing direction, and further includes at least one link between the portions that move in tandem.Type: GrantFiled: July 19, 2006Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Daniel N. Koury, Jr., Andrew C. McNeil
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Patent number: 7630693Abstract: A power amplifier (PA) line-up (210) and a method (500) for more efficiently utilizing battery power are disclosed. PA line-up (210) includes a driver (220), a matching circuit (214), and a PA (230) coupled to a matching circuit (216), wherein matching circuit (216) is configured to be coupled to a filter (260). PA line-up (210) includes a transmission line (260) coupled to matching circuit (216) and a switch (262) configured to selectively couple driver (220) to either matching circuit (214) or matching circuit (216) such that signal (205) is capable of by-passing PA (230) when signal (205) does not need to be amplified by PA (230). Furthermore, PA line-up (210) may include a second transmission line (250) so that signal (205) is capable of by-passing a driver (220) and a PA (230) when signal (205) does not need to be amplified by driver (220) and PA (230).Type: GrantFiled: November 16, 2006Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Lianjun Liu, Ricardo A. Uscola
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Patent number: 7629709Abstract: A method for regulating a DC to DC converter of a portable device begins by sensing deactivation of a non-battery power source of the portable device, wherein an internal supply voltage is derived from the non-battery power source. The method continues by obtaining an initial regulation value for the DC to DC converter, wherein the initial regulation value is based on a battery voltage and the internal supply voltage. The method continues by enabling the DC to DC converter based on the initial regulation value, wherein the DC to DC converter converts the battery voltage into the internal supply voltage such that transitioning from the non-battery power source to a battery power source provides the substantially constant internal supply voltage.Type: GrantFiled: December 29, 2004Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Marcus W. May
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Patent number: 7631229Abstract: In one aspect, a data transmission rate of a message signal representing a bus message at a bus and a propagation delay between an occurrence of the message signal at a transmission output to the bus and an occurrence of the message signal at a receive input from the bus are determined. Bit error detection is selectively disabled responsive to a compatibility between the data transmission rate and the propagation delay. In another aspect, a bus line interface includes a transmit output and a receive input coupled to a bus line, a bit error detection module and a data rate module. The bus line interface also includes a bit error control module to selectively disable the bit error detection module based on a propagation delay between a signal and a reflected signal and based on a data transmission rate of the signal.Type: GrantFiled: April 24, 2006Date of Patent: December 8, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Benjamin J. Ehlers