Patents Assigned to Freescale
  • Publication number: 20100028801
    Abstract: In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 4, 2010
    Applicants: International Businesss Machines Corporation, Freescale Semiconductor Inc.
    Inventors: Steven J. Holmes, Xuefeng Hua, Willard E. Conley
  • Publication number: 20100031212
    Abstract: Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, performance relation, and cost relation, and to facilitate a designer's understanding and manipulation of this information. The domain-specific information from each domain is converted to objects in this unified data schema and stored in a unified database that is accessible to every domain, so that the impact of the current state in the device domain can be accessed and analyzed by a designer from any domain. This approach enables design data sharing and real-time collaboration between different electrical/electronic (E/E) design domains, thereby facilitating the realization of design data collaboration, design change management, and product lifetime management (PLM) and product data management (PDM) implementation.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yibing Dong, Salim Momin
  • Publication number: 20100030546
    Abstract: Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, performance relation, and cost relation, and to facilitate a designer's understanding and manipulation of this information. The domain-specific information from each domain is converted to objects in this unified data schema and stored in a unified database that is accessible to every domain, so that the impact of the current state in the device domain can be accessed and analyzed by a designer from any domain. This approach enables design data sharing and real-time collaboration between different electrical/electronic (E/E) design domains, thereby facilitating the realization of design data collaboration, design change management, and product lifetime management (PLM) and product data management (PDM) implementation.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yibing Dong, Salim Momin
  • Publication number: 20100030940
    Abstract: A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.
    Type: Application
    Filed: March 7, 2007
    Publication date: February 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Dror Gilad, Ori Goren, Alon Shoshani
  • Publication number: 20100030525
    Abstract: Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, performance relation, and cost relation, and to facilitate a designer's understanding and manipulation of this information. The domain-specific information from each domain is converted to objects in this unified data schema and stored in a unified database that is accessible to every domain, so that the impact of the current state in the device domain can be accessed and analyzed by a designer from any domain. This approach enables design data sharing and real-time collaboration between different electrical/electronic (E/E) design domains, thereby facilitating the realization of design data collaboration, design change management, and product lifetime management (PLM) and product data management (PDM) implementation.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yibing Dong, Salim Momin
  • Publication number: 20100029344
    Abstract: A detector for detecting the connection of an accessory including a microphone and/or the state of a switch associated with the microphone for a mobile device, wherein the detector comprises a first flag generator for time multiplexing the detection of a signal above a predetermined threshold for each of two comparators, such that for one time period one comparator output is detected and for a second time period the second comparator output is detected to thereby form a first flag; a second flag generator for determining the connection of microphone to thereby generate a second flag; a lookup table for determining the connection of the accessory and/or the state of the microphone switch from the first and second flags.
    Type: Application
    Filed: October 6, 2006
    Publication date: February 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Jerome Enjalbert
  • Patent number: 7656331
    Abstract: An audio output circuit includes a DAC module, a line out circuit, and a headphone amplifier circuit. The digital to analog conversion (DAC) module is coupled to convert an audio component of digitized multimedia data into an analog audio signal. The line out circuit is coupled to amplify the analog audio signal based on a line out volume setting. The headphone amplifier is coupled to amplify the analog audio signal based on a volume setting to produce an amplified analog audio signal.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthew D. Felder, Charles Eric Seaberg
  • Patent number: 7657682
    Abstract: A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Annette Pagan, Matthew D. Akers, Christine E. Moran
  • Patent number: 7657854
    Abstract: A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Himanshu Goel, Amit Sharma
  • Patent number: 7655502
    Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marc A. Mangrum, Kenneth R. Burch
  • Patent number: 7657757
    Abstract: The present disclosure relates generally to semiconductor devices and related methods of operation. A semiconductor device is disclosed that comprises at least one cipher interface (126, 128) to a plurality of different cipher hardware modules (112, 114, 116) and central mode control logic (130-138, 106) responsive to the at least one cipher interface (126, 128). The central mode control logic (130-138, 106) is configured to provide a cipher operation in accordance with a selected cipher mode (104) in connection with at least one of the plurality of different cipher hardware modules (112, 114, 116).
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Joel Feldman
  • Patent number: 7656045
    Abstract: A bond pad for an electronic device such as an integrated circuit makes electrical connection to an underlying device via an interconnect layer. The bond pad has a first layer of a material that is aluminum and copper and a second layer, over the first layer, of a second material that is aluminum and is essentially free of copper. The second layer functions as a cap to the first layer for preventing copper in the first layer from being corroded by residual chemical elements. A wire such as a gold wire may be bonded to the second layer of the bond pad.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chu-Chung Lee, Kevin J. Hess
  • Patent number: 7655550
    Abstract: A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: February 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James K. Schaeffer, David C. Gilmer, Mark V. Raymond, Philip J. Tobin, Srikanth B. Samavedam
  • Publication number: 20100019818
    Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.
    Type: Application
    Filed: August 3, 2006
    Publication date: January 28, 2010
    Applicant: Freescale Semiconductor Inc.
    Inventors: Michael Priel, Dan Kuzmin, Anton Rozen
  • Publication number: 20100019395
    Abstract: A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.
    Type: Application
    Filed: August 1, 2006
    Publication date: January 28, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Michel Zecri
  • Publication number: 20100019794
    Abstract: An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
    Type: Application
    Filed: November 22, 2004
    Publication date: January 28, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yossi Amon, Dimitri Akselrod, Eyal Segev
  • Publication number: 20100019944
    Abstract: An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.
    Type: Application
    Filed: October 13, 2006
    Publication date: January 28, 2010
    Applicant: Freescale Semiconductor , Inc.
    Inventors: Omid Oliaei, Alan Bannon, Anthony Dunne, Matthew R. Miller, Daniel O'Hare
  • Patent number: 7651918
    Abstract: Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity type and a first lattice constant spaced apart by a gap or trench (69), filling (108, 210, 308) the trench or gap (69) with a second semiconductor material (70) of a second, conductivity type and a second different lattice constant so that the second semiconductor material (70) is strained with respect to the first semiconductor material (66) and forming (110, 212, 312) device regions (80, 88, S, G, D) communicating with the first (66) and second (70) semiconductor materials and adapted to provide device current (87, 87?) through at least part of the strained second semiconductor material (70) in the trench (69).
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edouard D. de Frésart, Robert W. Baird
  • Patent number: 7652597
    Abstract: A decoder comprising a decoding element arranged to operate in a first mode for decoding a turbo encoded data stream and in a second mode for decoding a viterbi encoded data stream, wherein the decoding element is responsive to a first control signal for switching from the first mode to the second mode during decoding of a turbo code block and responsive to a second control signal for switching from the second mode to the first mode to allow continued decoding of the turbo code block.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gideon Kutz, Amir I. Chass
  • Patent number: 7651889
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch