Abstract: A processing device asynchronously enters a first mode in response to an application of power at the processing device. The processing device receives a wake signal at the processing device subsequent to entering the first mode. The processing device asynchronously enters a second mode from the first power mode in response to receiving the wake signal. A clock at the processing device is disabled in the first mode and enabled in the second mode.

Abstract: A system and method for performing a convolution operation in a multi-mode wireless processing system. The method can include loading an initial value and a stride value into an address generator, generating an address based on the initial value and the stride value, supplying the generated address to a series of memories, loading input data into a series of registers, multiplying the contents of each register with a value stored at the generated address in the memory associated with each register, adding up the resulting multiplication products, and generating output based on the resulting sum. The number of memories and registers are equal, each register having an associated memory.

Abstract: Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material including a mounting side and having a perimeter. The active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the perimeter of the mold material.

Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.

Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Abstract: A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second clock rate and in a manner for interleaving the previous frame companded A-channel and B-channel data into the NICAM standard required interleaved format, wherein the companded A-channel and B-channel data of the previous frame was temporarily stored during a previous frame into the second memory in a format other than an interleaved format according to NICAM standard requirements.

Abstract: An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.

Abstract: A capacitance detection circuit that compensates for the fluctuation of a reference voltage with a simple structure. A C-V circuit for a sensor element generates a detection signal by amplifying a capacitance change value of the sensor element by a predetermined gain based on a reference voltage. A voltage compensation circuit, which is connected to the C-V circuit and supplies a reference voltage to the C-V circuit, reduces the gain relative to a deviation amount when the reference voltage fluctuates by a predetermined deviation amount.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: An apparatus and method for communicating information within a network having one or more communication buses (5, 6, 7, 8), consisting of one or more elements (20, 30, 40) to maximise throughput and minimise CPU involvement by executing the following. Compare incoming message identifiers (14) against a set of predetermined identifiers (22). Transpose data sets (12) within the incoming message data frame and where necessary, save and/or transmit new frames as defined by operations dependent upon the incoming identifier. By utilising an optimal set of operands the memory requirement is satisfied by a minimal size of standard type.

Abstract: An analogue to digital converter (ADC) is provided which comprises an signal sampling device, a signal comparison device, and a digital signal generator. An analogue signal to be converted to a digital signal is input into the ADC, the signal sampling device produces samples of the analogue signal, the signal comparison device receives the analogue signal and the analogue signal samples, performs a comparison between them and outputs comparison signals, and the digital signal generator receives the comparison signals and uses them to generate a digital signal. The signal sampling device may produce voltage samples or current samples of the analogue signal.

Abstract: A test unit for testing the frequency characteristics of one or more components of a transmitter of modulated signals. The test unit includes a data source for generating a test pattern of data. A test unit output is connected to the data source and connectable to an input of one or more of the components, for inputting the test pattern of data to the one or more components. The test unit includes a memory in which a first predetermined data sequence and a second predetermined data sequence are stored. The data source is connected with an data input to the memory, and the data source is arranged to generating the test pattern of data including the predetermined data sequences.

Abstract: A method of converting a plurality of input signals on first and second converters, such that the first and second converters are both used when the plurality of signals comprises two signals, characterised in that said method comprises: selecting more than two input signals; determining the type of each selected signal; combining any signals having the same type to form a combined signal; converting one type of signal with the first converter; converting a second type of signal with the second converter wherein the first or second type signals is a combined signal.

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Abstract: A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.

Abstract: A memory includes at least one write bit line and a plurality of memory cells. The at least one write bit line is configured to carry a write bit signal. The plurality of memory cells are arranged in a column and are configured to be selectively coupled to the at least one write bit line. The plurality of memory cells are configured to be selectively read or written in a first phase of a cycle and selectively read or written in a second phase of the cycle using the at least one write bit line.

Abstract: A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.

Abstract: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.

Abstract: A digital amplifier and method are provided to convert digital base-band signals to a pair of digital switching waveforms switching at a carrier frequency to create a modulated RF signal. The digital amplifier contains variable frequency suppressed carrier PWM generators that produce in-phase and quadrature-phase differential signals, a mixer that combines the differential signals, a decoder that decodes the combined signals, and a power stage that receives signals from the decoder and provides an amplified signal at the carrier frequency using switches. The mixer combines the differential signals such that only one of the differential signals is output in a period. The carrier generators have integral noise shaping and use a random period signal to re-distribute quantization noise to a band outside an RF band of interest and reduce EMI of the RF signal.