Abstract: A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

Abstract: A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal v

Abstract: Amplifier apparatus comprising a power amplifier having an operating frequency in the radio frequency or microwave or higher ranges and a pre-distorter, the characteristics of the power amplifier comprising a distortion from a linear transfer function. The pre-distorter comprises a non-linear path and a linear path including amplifiers having substantially identical physical characteristics, an input divider responsive to an amplifier input signal for applying respective pre-distorter input signals to the paths, and an output coupler for combining the signals from the linear path and the non-linear path to produce a pre-distorted signal. The characteristics of the pre-distorter comprise a distortion relative to a linear transfer function that compensates for the distortion of the transfer function of the power amplifier.

Abstract: An integrated circuit comprising a plurality of circuits is provided. The integrated circuit further comprises a plurality of power circuits, wherein each of the plurality of power circuits can supply a selected voltage to at least one of the plurality of circuits.

Abstract: A MEMS device that has a sensitivity to a stimulus in at least one sensing direction includes a substrate, a movable mass with corner portions suspended in proximity to the substrate, at least one suspension structure coupled approximately to the corner portions of the movable mass for performing a mechanical spring function, and at least one anchor for coupling the substrate to the at least one suspension structure. The at least one anchor is positioned approximately on a center line in the at least one sensing direction.

Abstract: In one embodiment, a method of programming an oscillator circuit includes providing a resonator, a first programmable capacitor, a second programmable capacitor, and an amplifier. The first programmable capacitor and the second programmable capacitor may be programmed at a first capacitance value during a first time period, wherein the first programmable capacitor provides a first voltage to bias the resonator and the amplifier alters the second voltage to provide a third voltage to the resonator. During a second time period the first capacitance value is increased.

Abstract: A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and a portion (50) of a collector region (82, 64, 62, 50) of the bipolar device (103) in a second portion (42) of the substrate (46), covering the MOS device (105) with differentially etchable dielectric layers (56, 58) and the combination with an etch-stop layer (68), completing formation of the bipolar device (103) without completely removing the etch-stop layer (68) from the MOS device (105), anisotropically etching the differentially etchable layers (56, 58) to form a gate sidewall (56?, 58?) of the MOS device (105), and applying contact electrodes (98) to the MOS (105) and bipolar (103) devices.

Abstract: A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Abstract: A method for enabling at least a portion of a multiple function handheld device begins by enabling at least a portion of a digital audio functionality in response to a first mode selection. The method continues by disabling wireless communication functionality in response to the first mode selection.

Abstract: Methods and apparatus for softstarting a voltage regulation circuit. A circuit for generating an output voltage at an output thereof includes a capacitor having a first terminal configured to be coupled to a reference potential and having a second terminal coupled to the output, and a switchable current source coupled to the capacitor for intermittently charging the capacitor until the output voltage is reached.

Abstract: Methods and corresponding systems for allocating processing resources for a number of instances (N) of a software component include determining an average processing cost (?) and a variance (?2) for the software component. Then a processing cost for the software component is estimated as a function of N, the average processing cost (?), and the variance (?2), and processing resources are allocated in response to the estimated processing cost. The software component can be partitioned into a number of blocks (L), wherein the L blocks include a required block and one or more optional blocks. In some embodiments in response to a total estimated processing cost exceeding an available processing value, selected optional blocks can be disabled to reduce the total estimated processing cost to a value equal to or less than the available processing value. The optional blocks can be prioritized and disabled in order of priority.

Abstract: Parasitic coupling effects between RF or microwave transistors provided in a common package are compensated by connecting one or more capacitors between the transistors. By connecting the capacitor(s) at a location that corresponds to the site of the coupling, the compensation is effective over a wide frequency band. This coupling-compensation makes it feasible to provide, in a common package, RF or microwave transistors intended to operate in quadrature, thereby improving performance matching and operating efficiency of the overall device.

Abstract: A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.

Abstract: By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or N well doping (25) used for the transistor base (581). This provides a hump-shaped base (583, 584) region with an adjustable base width (79), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (101-104) alone. By further partially blocking the source/drain doping step (107) used to form the emitter (74) of the bipolar transistor (80), the emitter shape and effective base width (79) can be further varied to provide additional control over the bipolar device (80) properties. The embodiments thus include prescribed modifications to the masks (57, 62, 72, 46) associated with the bipolar device (80) that are configured to obtain desired device properties.

Abstract: Disclosed are example open channel detection techniques at a light emitting diode (LED) driver of an LED system. The LED driver does not enable its LED channels before normal operation so as to inhibit current flow through the LED channels during start-up. While the LED channels are disabled, the LED driver compares the voltages at the LED channel inputs with a predetermined voltage to determine whether an operational LED string of an associated LED panel is connected to the LED channel. In the event that an LED channel is determined to be an “open” channel, the LED driver further disables the LED channel for the following normal operational mode. Otherwise, if the LED channel is determined to be connected to an operational LED string, the LED driver enables the LED channel for the normal operational mode, during which the LED channel can be selectively activated for light output subject to display data for the LED panel.

Abstract: A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal.

Abstract: A voltage regulator includes a first multi-gate transistor, a differential stage, a second stage having a second multi-gate transistor, and a pass transistor to apply an output voltage and output current to a device load. Based on a feedback voltage associated with the output voltage, the differential stage modulates a bias voltage applied to a control electrode of the pass transistor. A first gate of the second multi-gate transistor generates a nominal bias current for the pass transistor, and the second gate adjusts the bias voltage based on an output of the differential stage so that transients in the regulator output voltage resulting from sudden changes in current drawn by the device load are reduced.

Abstract: A pre-driver for driving a high-side transistor of a bridge driver is connected to a bridge driver including first and second drive transistors connected in series between a high voltage power supply and ground. A reference circuit generates a reference voltage that varies depending on the output voltage of the bridge driver. In response to the reference voltage, the regulator circuit generates an internal power supply voltage that is substantially higher than the output voltage by a constant value. A buffer circuit generates a drive voltage for driving the first drive transistor based on the internal power supply voltage and the output voltage.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: A data communication network, includes a transmitting node; a receiving node; and a connection between the transmitting node and the receiving node. The receiving node is arranged to process data received from the transmitting mode via the connection. The network further includes a first measuring unit which is connected with a measuring input to the receiving node. The first measuring unit can determine a first parameter value forming a measure for the data processing capacity of the receiving node. A calculator has an input connected to an output of the measuring unit and can derive from the first parameter value a second parameter value forming a measure for the transmission rate of data from the transmitting node to the receiving node. A transmission control unit has a transmission control input connected to a calculator output and a transmission control output connected to the transmitting node.