Abstract: A power amplifier (PA) line-up (210) and a method (500) for more efficiently utilizing battery power are disclosed. PA line-up (210) includes a driver (220), a matching circuit (214), and a PA (230) coupled to a matching circuit (216), wherein matching circuit (216) is configured to be coupled to a filter (260). PA line-up (210) includes a transmission line (260) coupled to matching circuit (216) and a switch (262) configured to selectively couple driver (220) to either matching circuit (214) or matching circuit (216) such that signal (205) is capable of by-passing PA (230) when signal (205) does not need to be amplified by PA (230). Furthermore, PA line-up (210) may include a second transmission line (250) so that signal (205) is capable of by-passing a driver (220) and a PA (230) when signal (205) does not need to be amplified by driver (220) and PA (230).

Abstract: A switching amplifier includes a power stage, a low pass filter, a combining circuit, and a feedback correction circuit. The power stage has an input terminal and an output terminal. The low pass filter has an input terminal coupled to the output terminal of the power stage, and an output terminal for providing a filtered pulse width modulated signal. The combining circuit has a first input terminal coupled to the output terminal of the power stage, a second input terminal coupled to the output terminal of the low pass filter, and an output terminal. The feedback correction circuit has a first input terminal for receiving a reference pulse width modulated signal, a second input terminal coupled to the output terminal of the combining circuit, and an output terminal coupled to the input terminal of the power stage.

Abstract: A method for regulating a DC to DC converter of a portable device begins by sensing deactivation of a non-battery power source of the portable device, wherein an internal supply voltage is derived from the non-battery power source. The method continues by obtaining an initial regulation value for the DC to DC converter, wherein the initial regulation value is based on a battery voltage and the internal supply voltage. The method continues by enabling the DC to DC converter based on the initial regulation value, wherein the DC to DC converter converts the battery voltage into the internal supply voltage such that transitioning from the non-battery power source to a battery power source provides the substantially constant internal supply voltage.

Abstract: Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (52, 52?) combined with associated drive or sense transistors (53, 141) to form an integrated MRAM array. The MRAM array has lower electrodes (602, 150, 160, 162) of the MRAM bits (52, 52?) formed substantially directly on a source or drain region (56, 142, 152-2) of associated drive or sense transistors (53, 141), so that the intervening vias (302, 34, 36) and underlying interconnects layers (332, 35) of the prior art (20) can be eliminated. An interconnect layer (65) is provided above the MRAM bit (52, 52?) and transistor (53, 141) combination (50, 125, 129, 133) for coupling upper electrodes (41, 164) of the MRAM bits (52, 52?) and other electrodes (601, 58, 152-1, 152-3, 186-1, 186-3) of the transistors (53, 141) to other elements of the array.

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80?, 80?), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44?, 84, 84?) and drift (50, 50?, 90, 90?) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50?, 90, 90?) at least into the underlying body region (44, 44? 84, 84?), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50?, 90, 90?).

Abstract: An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry. A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.

Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Abstract: A memory device includes a bit cell including an adjustable transmittance component having a first side and a second side. The adjustable transmittance component has an adjustable transmittance state representative of a bit value of the bit cell. The memory device further includes a photon detector optically coupled to a second side of the adjustable transmittance component. A technique related to the memory device includes determining a transmittance state of the adjustable transmittance component and providing a bit value for the bit cell based on the transmittance state. Another technique related to the memory device includes determining a bit value to be stored at the bit cell and configuring the adjustable transmittance component to have a transmittance state corresponding to the bit value.

Abstract: A method and a device are provided for controlling operation of a wireless device (200). The method (500) includes transmitting an initial signal (410) to a controller device (120) in an initial mode (505); receiving initial instructions (420) from the controller device in the initial mode, after transmitting the initial signal (510), the initial instructions identifying an operational mode; setting transmit and receive circuitry in the wireless device to transmit and receive according to the operational mode (515, 520, 525); and transmitting operational signals (430) in the operational mode (530). The wireless device 200 includes an antenna controller (290) and an antenna switch (225) for implementing this method.

Abstract: A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled to receive test data directly from the plurality of test points, and a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result. In one aspect, the at least on staging storage element has a plurality of staging storage elements wherein each of the plurality of staging storage elements corresponds to a different pipeline stage of the data processing system. In another aspect the MISR result is independent of varying memory access times.

Abstract: A controllable equalizer is arranged to be automatically and selectively disabled and is configured to operate in a frequency modulated (FM) radio receiver. The controllable equalizer includes an equalizer (115) that is configured to perform an equalization algorithm, e.g., CMA, that relies on a predetermined distribution for a received signal, where the received signal is available from the FM radio receiver and a spurious signal detector (123) that is configured to determine whether a spurious signal is present in the received signal and to disable the equalizer when the spurious signal is present.

Abstract: A control loop has a control slope associated therewith. The control loop is provided to control a unit under control. A method of regulating the control slope comprises the step of measuring the control slope of the control loop and modifying a parameter associated with the unit under control in order to maintain the control slope within a desired range. Lock of the control loop is therefore maintained.

Abstract: A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: A method for determining a bandwidth of a complex valued sample stream may include correlating a first portion of a preamble symbol of the complex valued sample stream with a second portion of the preamble symbol to generate a time autocorrelated portion. The method may further include transforming the time autocorrelated portion to generate a frequency diverse autocorrelated portion. The method may further include determining a first phase variance over a first region of the frequency diverse autocorrelated portion, wherein the first region has a first bandwidth. The method may further include determining a second phase variance over a second region of the frequency diverse autocorrelated portion, wherein the second region has a second bandwidth greater than the first bandwidth. The method may further include determining the bandwidth of the complex valued sample stream by comparing the first phase variance with the second phase variance.

Abstract: A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: A memory device includes a latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal. The memory device further includes a bit cell including a storage component, and a write row driver configured to enable write access to the bit cell to store the latched bit value at the storage component for a first phase and a second phase of a cycle of the clock signal, the second phase following the first phase, and a read row driver configured to disable read access to the bit cell for the first phase of the cycle of the clock signal and to enable read access to the bit cell for the second phase of the cycle of the clock signal.

Abstract: Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.

Abstract: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.