Abstract: A method that includes defining a transmission schedule of a TDM data frame that includes multiple TDM time slots allocated for transmitting data over a TDM line; the method is characterized by including: providing a transmission clock signal having a transmission clock frequency to the TDM line, providing a first clock signal having a first clock frequency to data sources that belong to a first group of data sources and providing a second clock signal having a second clock frequency to data sources that belong to a second group of data sources; wherein the first clock frequency and the second clock frequency are higher than the transmission clock frequency; pre-fetching, to a first intermediate storage a data segment from a data source out of the first group of data sources in response to a fullness level of the first intermediate storage unit and to the transmission schedule; pre-fetching, to a second intermediate storage a data segment from a data source out of the second group of data sources in response

Abstract: A disclosed self regulating biasing circuit (SRBC) includes an unregulated node that couples to an unregulated power supply that produces a supply voltage. An impedance element of the SRBC carries an unregulated current having a nominal component and a variance component between an unregulated node and a regulated node. A detection circuit connected between the unregulated node and a third node detects a variance component of a supply voltage and generates a detection current based on the variance component. A compensation circuit connected to the third node draws a compensation current, based on the detection current, from the regulated node. The SRBC is designed wherein the compensation current is approximately equal to the variance component of the unregulated current. The regulated node may be connected to a control terminal of a transistor to be biased.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length. In addition, the circuit comprises an element configured to selectively replace the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath. In one embodiment, the second channel length is a sub-minimal geometry with respect to the first channel length.

Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.

Abstract: Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

Abstract: A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-gate fin-type field effect transistor (multi-gate FinFET) of the device. A second gate of the multi-gate FinFET transistor receives a bias signal that provides a phase detection threshold. A phase adjustment signal is provided at one or both of the FinFET current electrodes based on the phase difference signal and the bias signal.

Abstract: A power on detection circuit for accurately detecting an input voltage with a simple circuit structure and reduced current consumption includes a voltage conversion circuit, which converts input voltage into current, and a latch circuit, which holds the power on detection signal. The voltage conversion circuit supplies output current to a current source and a capacitor via a connection node. The current source generates a flow of current that is proportional to the absolute temperature. When the output current of the voltage conversion circuit becomes greater than the current of the current source, the capacitor is charged and the voltage at the connection node is pulled up. A latching circuit is activated in accordance with the voltage at the connection node to output a power on detection signal.

Abstract: A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

Abstract: A differential capacitive sensor (50) includes a movable element (56) pivotable about a rotational axis (60). The movable element (56) includes first and second sections (94, 96). The first section (94) has an extended portion (98) distal from the rotational axis (60). A static layer (52) is spaced away from a first surface (104) of the moveable element (56), and includes a first actuation electrode (74), a first sensing electrode (64), and a third sensing electrode (66). A static layer (62) is spaced away from a second surface (106) of the moveable element (56) and includes a second actuation electrode (74), a second sensing electrode (70), and a fourth sensing electrode (72). The first and second electrodes (64, 70) oppose the first section (94), the third and fourth electrodes (66, 72) oppose the second section (96), and the first and second electrodes (68, 74) oppose the extended portion (98).

Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Abstract: A wireless communication system comprises a broadcast transmitter broadcasting textual and multimedia information to a remote receiver unit. The broadcast transmitter is operably coupled to a signal manipulation function and arranged to receive and process a broadcast signal that comprises both a textual portion and multimedia information. The signal manipulation function separates the textual and multimedia information into multiple bursts of data sub-blocks, wherein substantially each sub block comprises the textual data and a sub-block of multimedia information for transmitting to the remote receiver unit. By implementing the aforementioned inventive concepts, faster access to the most important (i.e. semantic) part of the transmitted information can be obtained.

Abstract: Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

Abstract: An integrated circuit (103) having a plurality of integrated circuit portions (111, 113, and 115) where each of the plurality of integrated circuit portions receives a corresponding voltage of a plurality of voltages. Selection circuitry (127 and 123) selects a selected voltage of the plurality of voltages and provides an indication of the selected voltage to adjust the supply voltage to the integrated circuit. in one embodiment, the indication may correspond to an analog signal proportional to the selected voltage such as e.g. at the selected voltage or at a voltage less than or greater than the selected voltage. A power supply system (105), coupled to the integrated circuit, may be used to receive the indication of the selected voltage and adjust the supply voltage based on the indication.

Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.

Abstract: An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.

Abstract: Higher voltage device isolation structures (40, 60, 70, 80, 90, 90?) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24?). One or more dielectric lined deep isolation trenches (27, 27?, 27?, 27??) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22?) is found to occur preferentially where the buried layer (24, 24?) intersects the dielectric sidewalls (273, 274; 273?, 274?; 273?, 274?) of the trench (27, 27?, 27?, 27??). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42?, 62, 72, 82) of the same conductivity type as the buried layer (24, 24?), underlying the buried layer (24, 24?) at the trench sidewalls (273, 274; 273?, 274?; 273?, 274?).

Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

Abstract: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.

Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42?) in which adjacent or spaced-apart P (46, 46?) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42?) and is spaced apart from the wells (46, 46?, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42?) between the wells (46?, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42?) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42?) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.