Abstract: In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.

Abstract: A method for race prevention and a device that has race prevention capabilities. The method includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. The device includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and between a start point of a second scan mode activation period of the output latching logic.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: A spread spectrum switching regulator generally includes an reactive circuit portion coupled to the input terminal, a switching element coupled to the reactive circuit portion, and a control circuit portion coupled between the switching element and the output terminal. The switching element has a drive signal characterized by a duty cycle, and the reactive circuitry portion is configured to produce an output voltage at the output terminal responsive to the duty cycle of the drive signal. The control circuit portion is configured to spread the input power across multiple frequencies by adjusting the drive signal of the switching element, thereby reducing input current noise through spread spectrum techniques. The drive signal is responsive to a pseudo-randomly generated ramp signal.

Abstract: A structure (40) for holding an integrated circuit die (38) during packaging includes a support substrate (42), a release film (44) attached to the substrate (42), and a swelling agent (60). A method (34) of packaging the die (38) includes placing the die (38) on the substrate (42) with its active surface (52) and bond pads (54) in contact with the film (44). The agent (60) is applied over an adhesive coating (50) of the film (44). The agent (60) causes the adhesive (50) to swell into contact with the bond pads (54) and/or to form fillets (64) of adhesive (50) about the die (38). The die (38) is encapsulated in a molding material (72) and released from the substrate (42) as a panel (74) of dies (38). Swelling of the adhesive (50) about the bond pads (54) prevents the molding material (72) from bleeding onto the bond pads (54).

Abstract: A radio record module includes a radio data system (RDS) decoder module, that decodes a received RDS signal, that has an associated audio signal, into received RDS data. A record module produces a digital data file from the digital audio signal in response to a record signal. A catalog generation module generates catalog data associated with the digital audio file, the catalog data including an RDS parameter of the received RDS data. A memory module stores the digital audio file and the catalog data.

Abstract: A lock loop circuit (230) includes a floating ground loop filter circuit (302) and a precharge circuit (304). The floating ground loop filter circuit includes at least one capacitive element (326, 328). The floating ground loop filter circuit provides a steering signal (334) for a controllable oscillator circuit (306) in response to a precharge signal (347). The precharge circuit provides the precharge signal in response to lock loop enable information (226). The precharge circuit controls the floating ground loop filter to bypass the at least one capacitive element for a period of time (606) in response to the lock loop enable information.

Abstract: An electronic device can include a substrate (12) having a primary surface (14), a second surface (16, 22) opposite the primary surface (14), and an electrode (50). In one embodiment, the electrode (50) can lie adjacent to the second surface (22) and include, a barrier layer (54) lying between a conductive layer (56) and a metal-containing layer (52), wherein the metal-containing layer (52) includes a first metallic element and not a second metal element, and the barrier layer (54) includes the second metal element and not the first metallic element. In another embodiment, an adhesion layer (52) and a conductive layer (56) can each include a metallic element, and lie immediately adjacent to a barrier layer (54). In still another embodiment, a process for forming an electronic device can include removing a portion of the substrate (12) opposite a primary surface (14).

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: In an automotive system (300), a knock detection scheme is provided for detecting knock events in an internal combustion engine that are sensed by a transducer structure, such as a non-intrusive acoustic accelerometer sensor (310) to generate sensor signal information which is processed by a signal processing structure (312, 316, 318, 326) which extracts digital signal parameters from the sensor signal information to identify a predetermined pitch frequency (330) and any short-term energy increase (328) in the digital signal information which in combination are used to provide a positive indication of engine knock behavior. When a short term Fourier transform (324) is used to extract the digital signal parameters, time frequency resolution may be improved by appropriately windowing the digital signal being transformed.

Abstract: A method of processing data based on programmed instructions includes referencing a number of locations in memory by forming addresses and correct buffer mappings corresponding to separate buffers in the plurality of buffers, and communicating data from the referenced locations in memory to a processing unit. The processing unit concurrently receives inputs from the separate buffers in the plurality of buffers and outputs to another buffer in the plurality of buffers.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region, wherein the layer includes hydrogen and (ii) using gases containing hydrogen in a plasma for the subsequent device processing, wherein the semiconductor device is subject to an undesirable device characteristic alteration by hydrogen incorporation into the region. The method further comprises forming a hydrogen barrier layer overlying the region, wherein the hydrogen barrier layer prevents substantial migration of hydrogen made available due to the subsequent device processing into the underlying region. The method further includes performing the subsequent device processing.

Abstract: An integrated circuit (300/400) includes first and second power domains and a bank of input/output (I/O) cells (305/405) coupled to the first and second power domains. The bank of I/O cells (305/405) includes a first plurality of active clamps (374/445) for the first power domain and a second plurality of active clamps (384/425) for the second power domain wherein the first (374/445) and second (384/425) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element (425, 445) for a respective second power domain. According to another aspect, each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.

Abstract: A transmitter and a receiver are both initially assigned a starting time slot from a plurality of active time slots in a superframe structure. A controller sends instructions to the transmitter and receiver during a first superframe. These instruct the transmitter to transmit signals during an ending time slot in one or more unused time intervals in the superframes. If the transmitter receives these instructions, it immediately begins transmitting in the ending time slot. If the receiver receives the instructions, it listens for the signals during both the starting active time slot and the ending active time slot for a set number of consecutive superframes after the first superframe. If the receiver does not receive the instructions, it listens for the signals during the entire superframe until it hears instructions in a new superframe. If the transmitter misses more than the set number of superframes, it stops transmitting.

Abstract: Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53?) of a first composition having an upper surface (541), with a body portion (54) proximate the upper surface (541), a drift portion (46, 83) spaced apart from the upper surface (541) and a trench (49, 49?) having sidewalls (493) extending from the upper surface (541) into the drift portion (46, 83). A second semiconductor (56) adapted to provide a higher mobility layer is applied on the trench sidewalls (493) where parts (78) of the body portion (54) are exposed. A dielectric (70) covers the higher mobility layer (56) and separates it from a control gate (72) in the trench (49, 49?). Source regions (68) formed in the body portion (54) proximate the upper surface (491) communicate with the higher mobility layer (56).

Abstract: A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

Abstract: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to ?Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Abstract: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

Abstract: A semiconductor device having upright dielectric nanotubes at an inter-layer dielectric level and method of manufacturing such a device is disclosed. The use of a catalyst is proposed in the disclosed manufacturing flow that facilitates growth of upright dielectric nanotubes having ultra low-k values that form all or part of the dielectric material for an ILD. In one embodiment, carbon nanotubes form interlayer conducting vias. In another embodiment dielectric material nanotubes form reinforcing pillars. The integration of catalysts is proposed to accommodate both upright dielectric and upright conducting nanotube fabrication in the same layer.