Abstract: Techniques for dynamic headroom control in a light emitting diode (LED) system are disclosed. An output voltage is provided to drive a plurality of LED strings. A feedback controller monitors the tail voltages of the LED strings to identify the minimum tail voltage and adjusts the output voltage based on the lowest tail voltage. The LED strings grouped into subsets and the feedback controller is segmented such that, for a certain duration, a minimum tail voltage is determined for each subset. The minimum tail voltages of the subsets are used to determine the overall minimum tail voltage of the plurality of LED strings for the certain duration so as to control the output voltage in the following duration. The segments of the feedback controller can be implemented in separate integrated circuit (IC) packages, thereby facilitating adaptation to different numbers of LED strings by integrating the corresponding number of IC packages.

Abstract: Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive the LED strings. An LED driver monitors the tail voltages of the active LED strings to identify the minimum, or lowest, tail voltage and adjusts the output voltage of the voltage source based on the lowest tail voltage. The LED driver can adjust the output voltage so as to maintain the lowest tail voltage at or near a predetermined threshold voltage so as to ensure that the output voltage is sufficient to properly drive each active LED string with a regulated current in view of pulse width modulation (PWM) performance requirements without excessive power consumption.

Abstract: A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.

Abstract: An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.

Abstract: A test circuit tests a device under test (DUT) uses a first switching device and a second switching device. The device under test (DUT) has a terminal for receiving a test signal. The first switching device has an output terminal for use in coupling the test signal to the terminal of the DUT when the DUT is being tested. The first switching device is high impedance when the DUT is not being tested. The second switching device is high impedance when the DUT is being tested and couples a bias control signal to the output terminal of the first switching device when the DUT is not being tested. The bias control signal substantially tracks the test signal. Leakage from the first switching device when other DUTs are being tested is greatly reduced because the bias control signal results in little or no bias across the first switching device.

Abstract: An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.

Abstract: A FCCH Burst detector includes a tone detection filter centered at 67.7 KHz, a tone rejection filter centered at ?67.7 KHz, moving average power calculation for the two filter outputs, and a detection logic. A FCCH burst is detected when the ratio of the moving average power of the tone detection filter output to that of the tone rejection filter output is larger than a threshold for a period longer than a threshold. The FB tone end time is detected when the ratio falls back to a threshold or the moving average power of the tone detection filter output falls below a threshold of the average power of the tone detection filter output over a predetermined period. The tone detection filter and the tone rejection filter is implemented by first frequency-shifting the received signal by ?67.7 KHz and +67.7 KHz in parallel, then passing the two frequency-shifted signals through two separate low-pass filters.

Abstract: A method for determining a presence of a preamble for an orthogonal frequency division multiplexed (OFDM) complex valued sample stream may include capturing a portion of the OFDM complex valued stream and autoconvolving the portion of the OFDM complex valued sample stream to generate an autoconvolved portion. The method may further include determining a presence of a preamble in the OFDM complex valued sample stream if a peak is detected in the autoconvolved portion.

Abstract: An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.

Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Abstract: A lock loop circuit (230) includes a floating ground loop filter circuit (302) and a precharge circuit (304). The floating ground loop filter circuit includes at least one capacitive element (326, 328). The floating ground loop filter circuit provides a steering signal (334) for a controllable oscillator circuit (306) in response to a precharge signal (347). The precharge circuit provides the precharge signal in response to lock loop enable information (226). The precharge circuit controls the floating ground loop filter to bypass the at least one capacitive element for a period of time (606) in response to the lock loop enable information.

Abstract: A lock loop circuit (216) includes a precharge circuit (304), an oscillator circuit (306), and a calibration circuit (309). The calibration circuit includes at least one register (362). The precharge circuit provides a precharge signal (347). The oscillator circuit provides an output frequency signal (228) in response to a steering signal (334) that is based on the precharge signal. The calibration circuit, prior to the lock loop circuit entering a disabled mode of operation, determines a calibration value (368) for the precharge circuit based on the precharge signal and the steering signal. The calibration circuit stores the calibration value as a digital calibration value (370) in the register.

Abstract: In one embodiment, a reflowable layer 51 is deposited over a semiconductor device 10 and reflowed in an environment having a pressure approximately equal to that of atmosphere to form a seal layer 52. The seal layer 52 seals all openings 43 in the underlying layer of the semiconductor device 10. Since the reflow is performed at approximately atmospheric pressure a gap 50 which was coupled to the opening 43 is sealed at approximately atmospheric pressure, which is desirable for the semiconductor device 10 to avoid oscillation. The seal layer 52 is also desirable because it prevents particles from entering the gap 50. In another embodiment, the seal layer 52 is deposited in an environment having a pressure approximately equal to atmospheric pressure to seal the hole 43 without a reflow being performed.

Abstract: A wireless communication unit comprises a semiconductor power amplifier device and a bias control circuit therefor. The bias control circuit comprises a detector for detecting at least a portion of the RF input signal; and a buffer for buffering the detected RF input signal. The detector is arranged to provide at least one inverted signal of the RF input signal. A semiconductor amplifier device is connected to an output of the bias control circuit and arranged to use an inverted detected signal to extract current from the output. When applied to a Doherty amplifier design, the biasing circuit requires fewer components, for example no video (buffer) amplifier and no delay block are required in the RF path. This facilitates integration of the circuit on a semiconductor die.

Abstract: A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively.

Abstract: A current sensor senses the current at a sense transistor and generates an output current that is an accurate proportional representation of the current at the sense transistor. Furthermore, the sensed current is relatively independent of the resistive load of the feedback path at feedback control module to which it is applied. In one embodiment, the feedback control module uses the sensed current in a DC-DC voltage converter to regulate a voltage. The current sensor employs a pair of operational amplifiers to match a voltage at a current electrode of a transistor that generates the output current to a voltage at a current electrode of the sense transistor, such that an effective resistance of the transistor generating the output current is significantly higher than the resistive load of the feedback control module, thereby ensuring that the output current is relatively independent of the resistive load of the feedback control module.

Abstract: The invention concerns a network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network and are designed to adapt their local communication time schedule to the communication time schedule of at least one other network mode, prior to being integrated as active network nodes. A network node to be integrated checks the activity of other network nodes and if no activity is identified, sends out positional messages for other network nodes, said message being fixed by predetermination in its communication time schedule. If a network node cannot be integrated as a reference node, it can only be integrated as an active node if it adapts its local communication time schedule to that of the reference node after receiving positional messages and if a check as to whether its own communication time schedule agrees with the communication time schedules of at least some of the active network nodes proves positive.

Abstract: The invention refers to a method for monitoring a communication media access schedule of a communication controller (5) of a communication system (1) by means of a bus guardian (6). The communication system (1) comprises a communication media (2) and nodes (3) connected to the communication media (2). Each node (3) comprises a communication controller (5) and a bus guardian (6) assigned to the communication controller (5). Messages are transmitted among the nodes (3) across the communication media (2) based on a cyclic time triggered communication media access scheme.

Abstract: A micro electromechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact. A piezoelectric electrode is formed on the movable portion. The piezoelectric electrode causes the movable portion to move in response to a driver voltage. A piezo element is formed on the movable portion of the switch. The piezo element is for detecting movement of the movable portion between an open position and a closed position. The piezo element is also used to detect switch bouncing when the switch transitions from the open position to the closed position. In one embodiment, the piezo element is a piezoelectric element and in another embodiment the piezo element is a piezo-resistive element.

Abstract: An apparatus and method are provided for reducing noise in a capacitive sensor (200). One apparatus includes a gain stage (210) including an output, the gain stage configured to generate a first signal having a noise component and a second signal having a desired output component and the noise component, and a filtered-sampling stage (250) having an input coupled to the gain stage output, the filtered-sampling stage configured to sample the first signal, store the first signal, and subtract the first signal from the second signal to produce a desired output signal. A method includes generating a first signal having a first noise component of the gain stage (710), storing the first signal (725), generating a second signal comprising a desired output component and the first noise component (730), and subtracting the first signal from the second signal to produce a first output signal having the desired output component (750).