Abstract: The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.

Abstract: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.

Abstract: A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.

Abstract: A method for operating a memory device includes selecting a cell comprising an array of word lines, selecting a word line within said array and applying an operating voltage to said selected word line. A shielding voltage is also applied to the closest adjacent facing word line of said selected word line. This may prevent unintended, program, read, or erase of said unselected word line. The remainder of unselected word lines can be floated.

Abstract: An amplifier and method of amplifying a signal is presented. The amplifier contains a fixed gain stage, a digitally controllable gain stage, and a continuously variable attenuator connected between the fixed and controllable gain stages. The attenuator and controllable gain stage are controllable such that the gain of the controllable gain stage is decreased when the attenuation of the attenuator reaches a predetermined maximum value and the attenuation of the attenuator is reduced thereafter. The output power level of the amplifier remains constant.

Abstract: An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are stored in the instruction itself. If the priority selection bits (50) are not stored in the instruction itself, a portion of the instruction (302) may be used to store a location indicator which indicates where the priority selection bits (50) are located (e.g. register file 22).

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: A system and method is provided for processing a digital image. The system and method processes image data by correcting for roll-off variability in the digital image. The system and method corrects for roll-off in image data by determining for each pixel a roll-off contour in which the pixel resides and adjusting that pixel based upon its roll-off contour, which in turn, depends upon its location on the image plane.

Abstract: A semiconductor device and method has interconnects with adjoining reservoir openings. A dielectric layer is formed as part of an uppermost of the one or more interconnect layers. Openings formed in the dielectric layer result in modified portions of the dielectric layer along portions of sidewalls of the openings. The openings are filled with a conductive material, such as metal. An exposed portion of the dielectric layer is removed to form protruding pads of the conductive material extending above the dielectric layer. Reservoir openings are formed adjacent the protruding pads by removing the modified portions of the dielectric layer. When the semiconductor device is bonded with another device, either a wafer or a die, laterally flowing metal collects in the reservoir openings and ensures that a reliable electrical connection is made between the semiconductor device and the other device.

Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

Abstract: Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.

Abstract: A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad array layout of the at least one pad array as a function of a set of keywords. The control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords. The keywords each define at least (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, and (c) placement information of the test structures relative to one or more pad allocations of at least one pad array. The pad array layout is configured for enabling a fabrication of corresponding test structures in test chips.

Abstract: A radio record module includes a radio data system (RDS) decoder module that decodes a received RDS signal, that has an associated audio signal, into received RDS data. A memory module stores a record request, the record request having an RDS parameter. A comparison module compares the received RDS data to the RDS parameter of the record request and asserts a record signal when the received RDS data compares favorably to the RDS parameter. A recording module records the associated audio signal in response to the record signal being asserted.

Abstract: A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).

Abstract: A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. An encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.

Abstract: A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.

Abstract: A system and method (400) for producing a reference signal is provided. The method includes supplying (405) a first current to a diode, sampling (410) a first voltage across the diode, supplying (405) a second current to the diode, sampling (410) a second voltage across the diode, converting (415) the first voltage and the second voltage to a first digital value and a second digital value, and determining (420) a digital reference value from the first digital value and the second digital value. The first voltage is based on the first current, and the second voltage is based on the second current.

Abstract: A method for measuring the thickness of a layer is provided, comprising (a) providing a structure (101) comprising a first layer disposed on a second layer; (b) impinging (103) the structure with a first ion beam comprising a first isotope, thereby sputtering off a portion of the first layer which contains a second isotope and exposing a portion of the second layer; and (c) determining (105) the thickness of the first layer by measuring the amount of the second isotope which is sputtered off.

Abstract: A symmetrical differential capacitive sensor (60) includes a movable element (66) pivotable about a geometrically centered rotational axis (70). The element (66) includes sections (86, 88). Each of the sections (86, 88) has a stop (94, 96) spaced equally away from the rotational axis (70). Each of the sections (86, 88) also has a different configuration (104, 108) of apertures (102, 106). The configurations (104, 108) of apertures (102, 106) create a mass imbalance between the sections (86, 88) so that the element (66) pivots about the rotational axis (70) in response to acceleration. The apertures (102, 106) also facilitate etch release during manufacturing and reduce air damping when the element (66) rotates. Apertures (126, 128) are formed in electrodes (78, 80) underlying the apertures (102, 106) to match the capacitance between the two sections (86, 88) of movable element (86) to provide the same bi-directional actuation capability.

Abstract: In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not part of the original design and state diagram of the unmodified state machine. In one embodiment, a method and apparatus is provided for dynamically reconfiguring a plurality of test circuits in re-useable modules on an IC without modifying the controller state machine in the re-usable module.