Abstract: The test signal generator generates an analog and digital test signals to test a sigma-delta ADC which has an analog portion succeeded by a digital decimation filter. The test signal generator supplies a first digital test signal having a first particular number of bits N and a first particular bit rate RN corresponding to digital signals occurring after the digital decimation filter. A digital sigma-delta modulator converts the first digital test signal into a second digital test signal having a second particular number of bits M<N thereby corresponding to a digital signal occurring at an input of the digital decimation filter. A DAC converts the second digital test signal into an analog signal, and a filter to filter the analog signal to obtain an analog test signal for testing the analog portion.

Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.

Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

Abstract: A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

Abstract: A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state.

Abstract: There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can, for example, perform a transient simulation on the device only once, and then add frequency spreading with specific parameters by simulation. The resulting frequency spread signal can be observed. The designer can thus evaluate the reduction in electromagnetic emission level, and repeat this process by iteratively applying frequency spreading each time with specific parameters but without having to modify the schematic of the device and to perform another simulation of the device. The method according to this innovation is extremely rapid as the simulation of the design does not need to be repeated at each run of the frequency spreading simulation.

Abstract: A resource domain controller in a data processing system stores information that is used to group various resources, such as bus masters and peripherals, into common domains. Each group can be referred to as a resource domain and can include one or more data processor and peripheral devices. The resource domain information is then used to determine whether a particular access request from a data processor is authorized to access its intended target, e.g., one of the peripheral devices, by determining whether the access request and the intended target each belong to a common resource domain. If so, the access request is allowed, otherwise the access request is prevented from being successfully completed.

Abstract: There is provided a method of estimating a bit error rate in a transport channel of a wireless communication system. The method comprises the receiving a signal from a remote transmitter of the wireless communication system via a physical channel, the signal comprising data and noise forming a plurality of soft bits. The method further comprises the counting, during a period of time, a number of erroneous bits being those soft bits which have an amplitude below ?2A or above +2A with A being the average amplitude of the soft bits received. Next, the number of erroneous bits is divided by a number of total bits received during said period of time in order to obtain the bit error rate. This method provides a way to estimate the BER value without knowing the exact shape of the noise distribution. In an embodiment a selection is made between two estimation algorithms.

Abstract: A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

Abstract: A memory system has a decoder circuit that includes a first driver circuit having an input coupled to receive a first pre-decode signal. The first driver circuit includes transistors wherein a first current electrode of a first transistor is coupled to receive a second pre-decode signal. The decoder circuit includes a second driver circuit having an input coupled to receive a third pre-decode signal. The second driver circuit includes transistors wherein a first current electrode of a third transistor in the stack is coupled to receive the second pre-decode signal. A fifth transistor has a first current electrode coupled to an output of the first driver circuit, a second current electrode coupled to an output of the second driver circuit, and a control electrode coupled to a fourth pre-decode signal.

Abstract: For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.

Abstract: A gate drive circuit drives a control terminal of a power transistor and comprises: a drive terminal for electrically coupling the control terminal, a first reference source, a first switch arranged between the first reference source and the control terminal, a switch control circuit and a measurement circuit. The first switch is switched-on to turn-off the power transistor. The switch control circuit switches-off the first switch during a transition period to a fully off-state. The measurement circuit outputs a control signal to the switch control circuit in response to a value of a voltage at the control terminal measured when a discharge current flowing to the drive terminal has been reduced to a predetermined threshold, for switching-on the first switch if the measured value is smaller than a threshold voltage.

Abstract: Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

Abstract: A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

Abstract: A bond wire feed system has a wire tensioning unit with a chamber that has a wire inlet aperture and a wire outlet aperture. The wire inlet and outlet apertures have centers that are aligned with a central axis of the chamber. A clamp is positioned to receive a bond wire provided from the wire outlet aperture. The clamp has at least two jaws movable relative to each other and arranged to grip the wire to align a central axis of the wire with the central axis of the chamber. The jaws are also movable along the central axis of the wire in order to pull the wire through the wire tensioning unit.

Abstract: A safety critical apparatus comprises a set of safety relevant modules; one or more comfort modules having one or more user interfaces; and a distraction controlling device arranged to adapt at least one of the one or more user interfaces to a current situation of operation of the safety critical apparatus.

Abstract: An apparatus for sensing current of a vehicle battery employs an extended counting analog-to-digital conversion process (212) to a chopped and amplified voltage appearing across a low ohmic shunt resistor (203) placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier (209) by matching the gain to the dynamic range of the ADC (212) permits a high dynamic signal sensing.

Abstract: A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Abstract: A memory system includes a memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data. A secondary memory includes a plurality of entries, and each entry configured to store an address value of an address location of the memory and one or more error correction bits corresponding to the data stored at the address location of the memory. The error correction bits in the secondary memory can be used to correct errors in a subset of the memory having a different number of storage bits than the error correction bits in the memory.

Abstract: A method for detecting a race condition, comprising storing a seed value to a first global variable D; detecting a race condition when the second global variable A does not equal a first predefined value V1, wherein the second global variable A was set to the first predefined value V1 at the initiation event prior to storing the seed value; storing a second predefined value V2 to the second global variable A; detecting a race condition when the first global variable D does not equal the seed value; accessing a shared resource; and storing the first predefined variable V1 to the second global variable A.