Abstract: A series regulator circuit for supplying voltage with low current consumption without depending on the capacitance of a load. A constant current source, which is connected to an input voltage line, is connected to a ground voltage line via a bipolar transistor. The gate terminals of first and second n-channel MOS transistors are connected between the constant current source and the collector terminal of the bipolar transistor. The drain terminals of the first and second transistors are connected to the input voltage line. The source terminal of the transistor functioning as an output terminal is connected via a first resistor element to the source terminal of the first terminal, which is connected to a ground voltage line via second and third resistor elements. A connection node between the second and third resistor elements is connected to a base voltage of the bipolar transistor.

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks or other signal lines) to obtain an actual performance-based probability of failure (POF) for the overall circuit.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

Abstract: A method, device and computer readable medium for enabling and blocking communications with a remote device based on a distance of the remote device. The method on which the device and computer readable medium are based includes transmitting a message from a local device to a remote device via an ultra wide band (UWB) wireless medium and receiving a response from the remote device via the UWB wireless medium. The transmitting and receiving steps are preferably performed in accordance with a Media Access Control (MAC) protocol. A distance between the local device and the remote device is then determined based on a time between the transmitting of the message and the receiving of the response and a function, such as communicating with the remote device, is performed in the local device based on the distance determined. The communication between the local device and the remote device may be enabled or disabled depending on the distance that the remote device is from the local device.

Abstract: A method is provided for operating a dual-use wireless device. The method includes: receiving an external timing signal at a first wireless circuit in the device; synchronizing a first clock in the first wireless circuit with the external timing signal; sending a first internal timing signal from the first wireless circuit to a second wireless circuit in the device, after the synchronizing; and listening for a remote periodic control signal at the second wireless circuit for a set monitoring time, a start of the monitoring time being based on the first internal timing signal. The second wireless circuit sends an association request if the second wireless circuit hears the remote periodic control signal within the monitoring time, and sends a local periodic control signal if the second wireless circuit does not hear the remote periodic control signal within the monitoring time.

Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract: A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch.

Abstract: A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.

Abstract: A node (401) responsive to a TDMA protocol is provided. The node (401) can include a transceiver (403) and one or more processors (407) cooperatively operable with the transceiver (403). The processor (407) can be configured to facilitate receiving (413) one or more frames to be transmitted in a communication over the transceiver (403). The frame(s) can indicate a priority relative to other frames. The processor (407) can queue (415) the frame(s) in one of several queues in response to the priority. Each of the queues can correspond to a different priority. The queues are serviced (417), including processing the frame(s) in the queue(s).

Abstract: An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the first output node. A clock distribution system including multiple uniform adjustable buffers coupled between at least one root node and multiple destination nodes, where each uniform adjustable buffer is adjustable between a minimum delay and a maximum delay.

Abstract: A method is provided for generating a multiple band ultrawide bandwidth signal. In this method, an ultrawide bandwidth devices provides a first reference signal having a first reference frequency, and a second reference signal having a second reference frequency that is different from the first reference frequency. The device generates a first ultrawide bandwidth signal based on the first reference signal, and a second ultrawide bandwidth signal based on the second reference signal, creating two separate frequency bands. These two signals can be generated form the same base clock signal, allowing for significantly simpler implementation and modification.

Abstract: A method is provided for transmitting data. A first device generates a first signal having a first duty cycle, comprising a first gated-on portion and a first gated-off portion in a time slot; and a second device generates a second signal having second duty cycle, comprising a second gated-on portion and a second gated-off portion in the same time slot. The first gated-on portion is generated during a first segment of the time slot and the first gated-off portion is generated during a second segment of the time slot, while the second gated-on portion is generated during the second segment and the second gated-off portion is generated during the first segment. Media access control (MAC) can be used to further define positions within time slots and provide error correction, power control, and the like. A preamble can be transmitted at an increased power level to facilitate acquisition.

Abstract: A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.

Abstract: An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.

Abstract: An optimized battery usage circuit for a comprehensive system-on-a-chip includes a first DC-to-DC converter operable to convert a battery voltage into a supply voltage when an alternate power source is not coupled to the comprehensive system-on-a-chip. A second DC-to-DC converter is operable to convert an alternate power source voltage into the supply voltage when the alternate power source is coupled to the comprehensive system-on-a-chip.

Abstract: The invention relates to gain calibration in a transceiver unit (100) having a transmitter unit and a receiver unit and a feed back coupling (165) between these. A signal level measurement unit (163) measures signal levels of a feedback signal through either the receiver unit or through a signal level detector (167). A reference signal level of the feedback signal is set by adjusting the transmitter until the signal level measurement unit (163) measures a predefined value when connected through the signal level detector (167). An absolute value of the transmitter gain is then calibrated. The signal level measurement unit (163) is connected through the receiver unit and the absolute gain of the receiver is calibrated. A gain is changed either in the receiver or the transmitter unit. The relative signal level change of the feedback signal is measured and used to calibrate the gain step.

Abstract: Methods and apparatus are provided to enable a transceiver (200) or transmitter including a single PA line-up (210) to transmit signals having frequencies in two or more different frequency bands, and/or having two or more different modulation types, and/or having two or more different RF power levels. The single PA line-up includes at least one variable matching circuit (216) and a variable harmonic filter (240) to tune match and tune filter communication signals prior to transmission. The variable matching circuit and the variable harmonic filter each include at least one variable capacitive element (2160 and 2400) that switches ON/OFF depending on whether a low frequency signal or a high frequency signal is being transmitted. Each variable capacitive element includes separate direct current and radio frequency terminals to enable the single PA line-up to change signal modulation and/or RF power levels in addition to frequencies.

Abstract: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.