Abstract: In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.

Abstract: An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage.

Abstract: A device 20 includes a substrate 22 having an integrated circuit (IC) die 24 coupled thereto. A bond wire 28 interconnects a die bond pad 32 on the IC die 24 with an insulated bond pad 36. Another bond wire 38 interconnects a die bond pad 42 on the IC die 24 with another insulated bond pad 46. The bond wires 28 and 38 serve as radiating elements of a dipole antenna structure 64. A reflector 72 and director 74 can be located on the substrate 22 and/or the IC die 24 to reflect and/or direct a radiation pattern 66 emitted by or received by the antenna structure 64. A trace 82 can be interconnected between the insulated bond pads 36, 46 to form a folded dipole antenna structure 84.

Abstract: A device having a temperature sensor device is disclosed. The temperature sensor device includes a complementary to absolute temperature (CTAT) module and a reference module. Both the temperature sensor and the reference voltage module provide signals, that vary in a complementary relationship with the variation in temperature. While the signals can be voltages or currents, for purposes of discussion the signals are discussed in terms of voltages herein. The reference module provides a signal that has a relatively small variation with temperature as compared to the variation in a signal provided by the CTAT module. The signals are provided to a comparator, which provides a temperature control signal based on a comparison of the input signals.

Abstract: An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array (300). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply (310) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply (310) may be used in any desired context, not just memories.

Abstract: A method and device for gamma compensation.

Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Abstract: A circuit for detecting overcurrent flowing to an output transistor. A replica transistor generates a reference voltage that is in accordance with a reference current flowing from a constant current circuit. A voltage-current conversion circuit generates a determination reference current proportional to the reference current based on the reference voltage. A current-voltage conversion circuit converts the determination reference current to a determination reference voltage. A detector detects overcurrent flowing to the output transistor based on the determination reference voltage.

Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

Abstract: A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the conductive layer serves as programmable material, that in a low impedance state, electrically couples conductive structures. A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word.

Abstract: A receiver for receiving different types of signals includes a receiver input for receiving a receiver input signal. A signal converter can convert the receiver input signal into a receiver output signal. A receiver output is connected to a converter output of the signal converter, for outputting the receiver output signal The receiver has a control input via which controllable parameters of the receiver can be controlled. The receiver further includes a memory. The memory has a first memory part in which a first set of receiver control parameters values for the receiver are stored and a second memory part in which a second set of receiver control parameters values for the receiver are stored. The receiver being able to receive a selected type of signals when the receiver is set in accordance to a selected set.

Abstract: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.

Abstract: A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating parameters such as operating current, operating voltage, resistance, capacitance, timing characteristics and an operating mode. A set of one time programmable elements can be used to selectively store information for modifying operating parameters and replacing the defective memory cells with redundant memory cells.

Abstract: A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of sets has a corresponding replacement pointer within the plurality of replacement pointers, and the corresponding replacement pointer indicates a way of the set. A cache command is provided which specifies a set of the plurality of sets and which specifies a replacement way value. In response to the cache command, a current way value of the replacement pointer corresponding to the specified set is replaced with the replacement way value. The cache may further include way locking control circuitry which indicates whether or not one or more ways is locked. By indicating a locked way with the replacement way value, a locked way can be overridden and thus be used for a subsequent cache line fill.

Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.

Abstract: A circuit comprises a reference voltage generating circuit, a first switch, a second switch, and a capacitive element. The reference voltage generating circuit has an input and output terminal for providing a reference voltage. The first switch has a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal. The second switch has a first terminal coupled to the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal. The capacitive element has a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

Abstract: An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.