Abstract: An IP2 tuning circuit (404, 1004, 1104 and 1404) for tuning the IP2 of a mixer (414 and 415) to minimize second order intermodulation distortion (IMD2) in a receiver (402, 1002, 1102 and 1402) of a transceiver (401, 1001, 1101 and 1401). An operating characteristic of the mixer related to IMD2 is changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD2. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit (1468).

Abstract: A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.

Abstract: A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in respective corresponding fields of the at least two registers to create a plurality of condition values. Second control circuitry performs one or more predetermined logic operations on less than all of the plurality of condition values and on more than one condition value of the plurality of condition values to generate a condition code for each of the one or more predetermined logic operations. A condition code register stores the condition code for each of the one or more predetermined logic operations.

Abstract: A method for reducing adjacent channel interference begins by determining a desired channel of a radio frequency (RF) signal. The method continues by determining a plurality of potential local oscillations for the desired channel. The method continues by determining a proximal power level of an image frequency of each of the plurality of potential local oscillations to produce a plurality of proximal power levels. The method continues by selecting one of the plurality of potential local oscillations for down converting the desired channel based on the plurality of proximal power levels.

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract: A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.

Abstract: A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

Abstract: A switching circuit includes (a) a bridge circuit (122) with a first output (266) to drive a load (130); and (b) a driver circuit (120) comprising a pair of cascode amplifiers (250, 251) receiving complementary inputs and a bias voltage, wherein the driver circuit (120) is electrically coupled to the bridge circuit (122).

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).

Abstract: A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant (215) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide (225) is formed which extends over the first and second lateral portions of the gate.

Abstract: A NICAM encoding method comprises performing NICAM processing and coupling a front-end to the NICAM processing. The front-end processing operates with a system clock that is integer divisible such that the system clock can be used by both the NICAM processing and the front-end processing. The front-end processing includes a front-end input processing and a front-end output processing. The front-end input processing is coupled to an input of the NICAM processing and the front-end output processing is coupled to an output of the NICAM processing.

Abstract: A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.

Abstract: A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

Abstract: A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode.

Abstract: An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.

Abstract: A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points.

Abstract: MEMS piezoelectric switches 100 that provide advantages of compact structure ease of fabrication in a single unit, and that are free of high temperature-induced morphological changes of the contact materials and resultant adverse effects on properties. High temperature-induced morphological changes refer to changes that occur during fabrication when metallic contacts such as radio frequency lines 125, 130 and shorting bars 150 are exposed to temperatures required to anneal a piezoelectric layer or those temperatures encountered during high temperature deposition of the piezoelectric layer, if such process is used instead.

Abstract: Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.

Abstract: A circuit for adjusting a magnitude of a transmit signal includes a transmitter (105), providing a transmit signal (107). It also includes a transmitter amplifier (109), receiving the transmit signal (107) and a power control adjustment signal (121), and responsive thereto, providing an amplified transmit signal (111). The circuit also includes a detector (123), for detecting an amplitude of the amplified transmit signal (111). Also included is an error component (137) for determining the difference between the amplitude and a reference level (129). Further provided is a digital signal generator (155), receiving the difference (145), and responsive thereto, generating (157) a reference signal (125) and the power control adjustment signal (117, 121), where the reference level (129) is responsive to the reference signal (125).

Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a <110> crystallographic orientation and a second semiconductor layer (405) having a <100> crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.