Abstract: A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60), determining access permissions (86) based on the access request (84), and selectively modifying the access permissions based on the state information (90). The state information (60) may relate to debug operation, operation from unsecure or unverified memories, memory programming, direct memory access operation, boot operation, software security verification, security levels, security monitor operation, operating mode, fault monitor, external bus interface, etc (88).

Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.

Abstract: “Electrical field (“E-field”) sensor systems that sense displacement or change in displacement of one body relative to another.” In general, the bodies 110, 112 are within an electrical field and displacement of a body causes a change in the E-field. A field sensor 290 detects this change and a processor 275 translates it to a change in position of the displaced body 110. The E-fields are generated by electrodes (or an electrode and a ground member) that generate the E-field. The systems include detectors 240 that detect changes in the E-field, such as capacitance, and transmit these to the processor 275.

Abstract: An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.

Abstract: A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device sample possibly including a failure area having wicked in encapsulation material containing the dye. The prepared device sample is then sectioned to facilitate viewing a cross section face of the device under inspection. Lastly, a dark field analysis on the prepared device sample is performed with the use of dark field illumination. Responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained.

Abstract: Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

Abstract: A semiconductor device has two types of multi-gate transistors, N channel and P channel, in which each type has a bottom gate and a top gate. The bottom gate and the top gate of the N channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the N channel transistors. Similarly, the bottom gate and the top gate of the P channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the P channel transistors.

Abstract: An oscillator circuit having a relatively simple circuit structure while enabling full swing with low power consumption includes an oscillation core block, a voltage restriction block, and a differential output block. Drain terminals of first and second transistors are each connected to the voltage restriction block. The voltage restriction block restricts the amplitude of an oscillation signal to a reference voltage. Source terminals of third and fourth transistors are connected to drain terminals of fifth and sixth transistors, and source terminals of seventh and eighth transistors are connected to drain terminals of ninth and tenth transistors. This supplies the differential output block with current generated by the amplitude restriction. The differential output block converts the current into drive voltage to ground voltage to perform full swing.

Abstract: A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Abstract: A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.

Abstract: A memory not only uses redundant cells but also redundant references to reduce the likelihood of a failure. In one approach a failure in a reference can cause both the primary cell as well as the redundant cell to be ineffective. To overcome this potential problem two references for each bit are employed. In one form, the primary cell of a first bit is compared to one reference and the redundant cell of the first bit is compared to another reference. The primary and redundant cell of a second bit can use these two references as well. In another aspect, two references are placed in parallel for both the primary and redundant cell of the bit.

Abstract: Methods and apparatus are provided for use in manufacturing a device packaging comprising the steps of: positioning a metal substrate such as spring steel on a magnetic plate so as to expose a surface of the metal substrate; placing a first tape layer on the exposed surface of a metal substrate so as to expose a nonstick surface of the first tape layer such as PTFE; placing a second tape layer on the exposed surface of the first tape layer so as to expose a surface of the second tape layer; positioning a mold frame on the exposed surface of the second tape layer; positioning a die within the mold frame; depositing epoxy within the mold frame; curing the epoxy so as to create a molded panel; removing the mold frame; grinding the molded panel to a desired thickness; separating the first tape layer from the second tape layer so as to separate the metal substrate from the molded panel; and peeling the second tape layer from the molded panel.

Abstract: A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.

Abstract: A method (500) is provided for operating an interleaver circuit 120 having N shift lines (2201-220N). Each shift line has a line input node, a line output node, and one or more bit storage elements (240). The method includes: storing don't-care bits in each bit storage element (520); isolating the line output nodes from an interleaver output node (520); receiving a stream of data bits at an interleaver input node (530); and sequentially connecting the interleaver input node to respective line input nodes to shift the stream of data bits into the bit storage elements of corresponding shift lines in an interleaved fashion (530). A don't-care bit is shifted out of each of the bit storage elements in corresponding shift lines as each data bit is shifted in. A last don't-care bit is shifted out of respective bit storage elements in the shift lines during N consecutively-received data bits.

Abstract: A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer without removing a significant amount of the first stressor layer and also planarizing a boundary between the first stressor layer and the second stressor layer.

Abstract: A method for accessing a memory comprising a first set of bit columns, a second set of bit columns, and a redundant set of bit columns, wherein any one of the redundant set of bit columns can be substituted for one of the first set of bit columns or one of the second set of bit columns and wherein each of the bit columns can receive a read voltage or a write voltage, is provided. The method includes during a write operation to the first set of bit columns, providing the write voltage to one of the redundant set of bit columns, if the one of the redundant set of bit columns has been substituted for one of the first set of bit columns, otherwise providing the read voltage to the redundant set of bit columns.

Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Abstract: A method for forming a semiconductor device includes providing a semiconductor layer, forming a passivation layer over the semiconductor layer, wherein the passivation layer has an opening having sidewalls, forming a fin over the semiconductor layer, wherein after forming the passivation layer the fin is within the opening, and forming a portion of a gate within the opening. In one embodiment, a dummy gate is used. In one embodiment, spacers are formed within the opening of the passivation layer. The structure is also discussed.

Abstract: A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Abstract: A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device.