Abstract: A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.

Abstract: A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities.

Abstract: A magnetoelectronic device structure 20 includes programming lines 26 and 28 and a magnetoelectronic device 24 between the programming lines 26 and 28. In one embodiment, layers 38, 40, and 42 of a colloidal dispersion of an electrically insulating material and magnetic particles are positioned between the magnetoelectronic device 24 and the programming lines 26 and 28. The magnetic particles cause the colloidal dispersion to have an enhanced magnetic permeability property. The layers 38, 40, and 42 are disposed by a spin coating technique.

Abstract: A wireless subscriber communication unit comprises a transmitter having a power amplifier and a feedback power control loop having a power control function arranged to set an output power level of the power amplifier. The power control function is arranged to perform a back-off of the output power prior to completion of a transmission burst.

Abstract: An electronic device comprises a voltage regulator supplying a current to a load such as a micro-controller unit. The load controls the current provided to the load from the voltage regulator. Preferably, the load controls the level of current supplied to the load upon start-up, thereby avoiding power surges being drawn by the load.

Abstract: A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion of a floor of the first trench. The charge storage stack includes a layer of discontinuous storage elements (DSEs). Electrically conductive spacers formed on opposing sidewalls of the first trench adjacent to respective charge storage stacks serve as control gates for the device. The DSEs may be silicon, polysilicon, metal, silicon nitride, or metal nitride nanocrystals or nanoclusters. The storage stack includes a top dielectric of CVD silicon oxide overlying the nanocrystals overlying a bottom dielectric of thermally formed silicon dioxide. The device includes first and second injection regions in the layer of DSEs proximal to the first and second diffusion regions.

Abstract: A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.

Abstract: A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based on a state of the first word line and a state of the second word line. The memory device further comprises control logic to configure, for an access to the bit cell, the state of the first word line and the state of the second word line based on an access type of the access.

Abstract: A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Abstract: A method (700) and apparatus (600) are described for performing decision voting in connection with a parallel ACS unit (110) and track buffer (112) in an Ultrawide Bandwidth (UWB) receiver having a parallel DECODER for decoding a message sequence encoded according to a convolutional code. Outputs from the track buffer can be input to a voting unit (620) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: A system and method for obtaining processor diagnostic data. The method can include receiving a instruction, enabling write access of an output stream to a diagnostic memory, writing to the diagnostic memory at a first frequency, and reading from the diagnostic memory at a second frequency where the first frequency is greater than the second frequency.

Abstract: A small transceiver device and antenna system has an insulating layer with first and second surfaces. A transmit loop element having transmit loop segments is formed on the first surface. The transmit loop segments are disposed in a transmit zigzag configuration. A receive loop element having receive loop segments is formed on the second surface. The receive loop segments are disposed in a receive zigzag configuration. Each receive loop segment in the receive zigzag configuration is skewed with respect to a closest transmit loop segment disposed in the transmit zigzag configuration. The transmit loop segments can be grouped in two or more transmit zigzag configurations, and the receive loop segments can be grouped in two or more receive zigzag configurations.

Abstract: A reference circuit includes: (a) a first reference circuit having a reference signal and a ?VBE loop; and (b) a modification circuit using a first voltage to change a first current in the ?VBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit. In some embodiments, the reference circuit can include a bandgap core circuit, which adds a VBE and a multiplied ?VBE, so that the output voltage of the reference circuit is a bandgap voltage. The reference circuit also can also include a modification circuit, which uses the output voltage (i.e. the reference signal) of the bandgap core circuit to change a current in the ?VBE loop. The ?VBE loop can be the portion of the circuit involved in generating the ?VBE voltage. Other embodiments are disclosed in this application.

Abstract: An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A system for removing particles from a polishing pad to improve the efficiency of the removal of material by the polishing pad as part of a chemical-mechanical polishing process, the system comprising a polishing pad; a fluid dispenser arranged to dispense a fluid on the polishing pad; and removal means, wherein the removal means include a heater for increasing the temperature of the fluid dispensed on the polishing pad, and/or voltage means for coupling the polishing pad to a voltage source for repelling charged particles from the polishing pad surface while the fluid dispenser is dispensing the fluid on the polishing pad.

Abstract: A method for forming a semiconductor device, the method includes providing a semiconductor substrate, applying a slurry to the semiconductor substrate, wherein the slurry was tested using a testing method includes taking a first undiluted sample from a top of the slurry; determining a first particle size distribution characteristic of the first undiluted sample; taking a second undiluted sample from a bottom of the slurry; determining a second particle size distribution characteristic of the second undiluted sample; and comparing a difference between the first particle size distribution characteristic and the second particle size distribution characteristics with a first predetermined value.

Abstract: A method for cleaning, especially by removing etch residue (e.g., polymers or particles) from a semiconductor structure, and a cleaning chemistry is described. The method of cleaning includes placing the semiconductor structure with an etch residue particle on it in a chemistry to remove the particle, wherein the active component of the chemistry consists of a carboxylic acid having equal numbers of COOH and OH groups. In one embodiment, the carboxylic acid is tartaric acid. In one embodiment, the chemistry further comprises water.

Abstract: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.