Abstract: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the substrate (100) such that intermetallic interconnects (128) are formed between the capacitor (112) and the substrate (100).

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A method for searching within a data block for a data chunk having a predefined value, the method includes: fetching, by a processor, a data block search instruction; fetching, a data unit that includes multiple data chunks; wherein at least one data chunk within the data unit belongs to the data block; deciding whether to use a mask for data chunk level masking; searching, by a hardware accelerator, for a valid data chunk within the fetched data unit that has the predefined value; wherein the searching comprising applying a mask; wherein a valid data chunk in an non-masked data chunk that belongs to the data block; and determining whether to update the value of the mask and whether to fetch a new data unit that belongs to the data block.

Abstract: Known techniques for forming nanoparticles require a multiple-step process to coat a surface with nanoparticles. The present invention provides a single-step process that requires the deposition of a substrate in a mixture of a solvent, ligands and organometallic precursors. The mixture containing the substrate is heated under pressure in a dihydrogen environment for a predetermined period of time, during which supercrystals of nanoparticles form on the substrate.

Abstract: An integrated circuit (102) and method computes fixed point vector dot products (424) and/or matrix vector products using a type of distributed architecture that loads bit planes (add00-add30) and uses the loaded bit planes to generate a plurality of partial products (416-422) directly, such as without a lookup table, and the plurality of partial products are computed in real time and are not read out of addressable memory. In one example, pixel coefficients and corresponding data are loaded such that, for example, a bit plane is loaded to generate partial product results on a per bit plane basis. The plurality of partial products are then summed (414) or accumulated to produce fixed point vector dot product data (424).

Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

Abstract: An equalizer and corresponding methods is arranged and constructed to mitigate adverse effects of a wireless channel (300). The equalizer includes a delay line (503) coupled to an input signal (501) and comprising a delay circuit coupled to an output combiner (507) that is operable to provide an interim signal (g0 . . . gN) and a feed forward circuit (505) coupled to the delay line and operable to provide a feed forward signal (506) that comprises a hard decision scaled according to a scaling factor corresponding to an estimate of channel parameters, wherein the output combiner is operable to combine the feed forward signal and the interim signal to provide an output signal (509) that is compensated for an adverse effect of the wireless channel on the input signal.

Abstract: A sigma delta converter configured for DC offset correction is presented. The sigma delta modulator has integrator circuitry including an integrator input and an integrator output. An input signal received at the integrator input has an input AC voltage component and a DC offset component. Capacitors are connected to the integrator input, and a first set of switches is connected to the pair of capacitors. The first set of switches transfer a first charge to the pair of capacitors during a first phase, and a second set of switches transfer the first charge and a second charge to the integrator input.

Abstract: A wireless network is provided that uses pseudo-static time slots. These time slots remain fixed in time unless and until a network controller specifically changes them and the network controller subsequently receives confirmation of the change. Times and durations of the pseudo-static time slots are only changed in small steps as each relevant device in the network acknowledges the step. To aid in allowing full coverage even during a change of active devices, when a transmitter and receiver are moved to a new time slot, the receiver is set to listen to both the old and the new time slots until the transmitter confirms that it has made the switch.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard instruction portion of the standard instruction size and an augmented instruction portion. The augmented instruction portion provides additional capabilities associated with the standard instruction portion. The augmented instruction portion can provide capabilities associated with conditional execution of the standard instruction portion or other instructions within a program loop. Furthermore, the augmented instruction portion can provide an additional operand to be used with the standard instruction portion.

Abstract: One embodiment of the present invention relates to noise control of one or more signals. In one embodiment, impulsive-type noise events, such as multipath noise events or pops, may be detected and suppressed to reduce signal distortion. For example, in one embodiment related to a radio receiver (100), a predictor (436) having an adaptive filter (402) is used in combination with a fast attack slow decay mechanism (434) to provide noise control signals (352, 358) which may then be used to suppress noise events. In one embodiment, the fast attack slow decay mechanism includes applying a wide bandwidth filter at the onset of a noise event to quickly track variations in an error signal and applying a narrow wide bandwidth filter a peak of the noise event is detected in order to smooth variations in the error signal (410). This allows for improved psycho-acoustic perception. In one embodiment, the radio receiver is a mobile radio receiver.

Abstract: A power supply includes a switching circuit and a transient control module. The switching circuit is switched in accordance with a regulation signal to produce an output voltage. The adjustable feedback module is operably coupled to produce the regulation signal based on the output voltage. The transient control module adjusts the adjustable feedback module by a step adjust value to produce a present output voltage. The transient control module monitors the adjustable feedback module for a present adjustment to determine when the power supply substantially achieves a steady-state condition. When the power supply substantially achieves a steady-state condition, determining whether the present output voltage corresponds to the second output voltage level. When the present output voltage does not correspond to the second output voltage level, the adjust, the monitor, and the determine steps are repeated.

Abstract: A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e.g., the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: A system and method (700) of indicating remaining life of a Non Volatile Memory (NVM) Array can be implemented in an integrated circuit. The method includes estimating (703) the remaining life of an NVM array by characterizing one or more cells to provide an estimate; comparing (709) the estimate to a threshold to provide a comparison; and when the estimate satisfies the threshold, providing (711) an indication corresponding to the comparison. The system comprises an NVM array (201); a controller (202) configured to control the NVM array, to estimate remaining life of the NVM array by characterizing one or more cells, and to provide an output signal corresponding to life expectancy of the NVM array; and a register (215) to store a flag corresponding to the output signal, where the flag may be used to provide information corresponding to predicted life expectancy to a user.

Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.

Abstract: An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.

Abstract: A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.