Abstract: A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A method device and a method. The method includes fetching an instruction, decoding an instruction that includes an instruction type field, a first variable field, a second variable field, a result field and a constant field; selecting an operation out of addition operation, a subtraction operation and another type of operation, in response to the content of the instruction type field; determining, in response to the value of the constant field, whether the result of the selected operation is responsive to the first and second variables or is responsive to the first variable, the second variable and the constant; and executing the selected operation, during a single instruction execution cycle, to provide the result.

Abstract: A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit.

Abstract: An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Abstract: A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality of selectable temperature independent current sources for generating a temperature independent current, and a summer coupled to the temperature dependent current generator and the temperature independent current generator for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier. A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

Abstract: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region (63) defined in said fin and in said horizontal region.

Abstract: A method for scheduling a transmission of ATM cells, the method includes: receiving an indication that a scheduling session should starts; and repeating the stages of: selecting a channel representative queue out of multiple queues that are associated with different quality of service traffic threads that belong to that channel; scheduling a transmission of frames from channel representative queues and from single queue channels; wherein the scheduling comprises processing a scheduling table that comprises multiple sets of entries, wherein each set of entries is associated with a different transmission priority level, and wherein at least one set of entries comprises a link to a transmission parameter table that is associated with a channel representative queue.

Abstract: In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.

Abstract: Systems, methods, and apparatus for reducing dynamic range requirements of a power amplifier in a wireless device are provided. An exemplary method may include modulating a symbol stream to generate a modulated waveform. The exemplary method may further include generating at least one pulse having a peak aligned with an anticipated position of a peak or a null corresponding to the modulated waveform, where the anticipated position of the a peak or the null corresponding to modulated waveform may be determined by detecting a transition in a phase or an amplitude of the modulated waveform.

Abstract: A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of transistors are fabricated in the first region and the second region respectively. Third and possibly fourth regions of the active layer may be processed to alter their strain characteristics. A sacrificial strain structure may be formed overlying the third region. The strain structure may be a compressive. When annealing the wafer with the strain structure in place, its strain characteristics may be mirrored in the third active layer region. The fourth active layer region may be amorphized in stripes that run parallel to a width direction of the transistor strain to produce uniaxial stress in the width direction.

Abstract: A method and a device for exchanging data. The method includes: requesting the processor, by the data transfer controller, to initiate a transfer of multiple data chunks from the second memory unit to the Virtual FIFO data structure, in response to a status of the virtual FIFO data structure; sending the data transfer controller, by the processor a request acknowledgment and an indication about a size of a group of data chunks to be transferred to the virtual FIFO data structure; updating the state of the virtual FIFO data structure; transferring, by the second level DMA controller, the group of data chunks from the second memory unit to the virtual FIFO data structure; sending, by the processor a DMA completion acknowledgment indicating that the group of data chunks was written to the virtual FIFO data structure; and transferring, by a first level DMA controller, a data chunk from the virtual FIFO data structure to the hardware FIFO memory unit.

Abstract: A system for cleaning a conditioning device to improve the efficiency of the conditioning of a polishing pad using the conditioning device as part of a chemical-mechanical polishing process, the system comprising a conditioning device; a fluid dispenser arranged to dispense a fluid on the conditioning device; and an acoustic nozzle arranged to emit a megasonic or ultrasonic signal at the conditioning device while the fluid dispenser is dispensing the fluid on the conditioning device.

Abstract: A micellar solution is used to seal pores exposed at the bottom and sidewall surfaces of a structure etched in or through a porous low dielectric constant material. The micellar solution is also effective to clean away etch residues from the etched structure.

Abstract: A device having framing capabilities, the device includes at least one memory unit adapted to store data and metadata required for framing the stored data; the device is characterized by including a framer that is connected to a framed data unit and to a data fetch unit; wherein the device is adapted to select between a first operation sequence and a second operation sequence; wherein the first operation sequence comprises a data chunk and metadata fetch operation followed by a data chunk frame operation and wherein the second operation sequence comprises a multiple data chunk fetch operation followed by multiple data chunk frame operations; wherein the data fetch unit and the framer are adapted to execute the selected operation sequence. A method for framing data, the method includes storing data and metadata required for framing the stored data at one or more memory devices.

Abstract: A modulation system can switch between two modulation modes. In order to comply with limits on peak power in spectral bands outside the RF operating one the transmitter is required to ramp down to a condition of minimal power. To avoid fixed ramping and trailing bits, the transmitting signal is subjected to FIR filtering. The two FIR filters are primed with a sequence using a parallel input mode before serially entering the information data.

Abstract: Methods and apparatus are provided for reducing substrate leakage current of lateral RESURF diode devices. The diode device (60, 60?, 100) comprises first (39) and second (63) surface terminals overlying a semiconductor substrate (22) coupled to P (38, 32, 26) and N (24, 30, 46) type regions providing the diode action. An unavoidable parasitic vertical device (54, 92) permits leakage current to flow from the first terminal (39) to the substrate (22). This leakage current is reduced by having the diode device second terminal (63) comprise both N (46) and P (62) type regions coupled together by the second terminal (63). This forms a shorted base-collector lateral transistor (72) between the first (39) and second (63) terminals to provide the diode function. The gain of this lateral transistor (72) increases the proportion of first terminal (39) current that flows to the second terminal (63) rather than the substrate (22).

Abstract: An electric field sensor may be used to detect accumulation of frozen material. In one embodiment, an e-field system includes a first electrode, a second electrode located at a distance from the first electrode, the second electrode forming a capacitive element with the first electrode, wherein a gap is present between the first and second electrodes, and an electric field sensor having an electrode terminal coupled to the first electrode and providing an electric field output value representative of an amount of frozen material located in the gap between the first and second electrodes. The system may also include a first insulator adjacent the first electrode and outside the gap, and a conductive layer adjacent the first insulator, where the first insulator is between the first electrode and the conductive layer, and where a shield output of the electric field sensor is coupled to the conductive layer.