Abstract: A level shifter circuit includes first and second cross-coupled P channel transistors, first and second cross-coupled N channel transistors, and first and second inverters. The first and second P channel transistors are coupled to receive a first power supply voltage. The first and second cross-coupled N channel transistors are coupled to the first and second P channel transistors. The first and second inverters are coupled to the first and second N channel transistors and are coupled to receive a second power supply voltage that is lower than the first power supply voltage. The first and second N channel transistors have a lower, substantially zero volts, threshold voltage and can be controlled by a low voltage signal while limiting a leakage current.

Abstract: A method (500) is provided for operating a network coordinator (110). The method includes receiving device capability information from a plurality of network devices (121-125), including whether each of the network devices can perform network control functions (520); determining whether any of the network devices is capable of performing network control functions based on the device capability information (540); choosing one of the network devices that is capable of performing network control functions to be a designated next coordinator if any of the network devices are capable of performing network control functions (570); determining that there will be no designated next coordinator if none of the network devices are capable of performing network control functions (550); and sending a beacon (220) to the network devices, the beacon including next coordinator information (300) indicating one of: the designated next coordinator, or that there is no designated next coordinator (580).

Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.

Abstract: A method includes providing an in-phase signal and a quadrature-phase signal (I/Q signals), processing the in-phase and quadrature phase signals to produce a magnitude signal and a phase signal, conditioning the phase signal to produce a conditioned phase signal, filtering the magnitude signal to produce a filtered magnitude signal, and amplifying the conditioned phase signal as a function of the filtered magnitude signal to produce a polar modulated signal. An apparatus includes a pair of I/Q channels, an I/Q to magnitude/phase circuit coupled to the pair of I/Q channels, a magnitude conditioning circuit coupled to the I/Q to magnitude/phase circuit; the magnitude conditioning circuit embodying a magnitude filter; a phase conditioning circuit coupled to the I/Q to magnitude/phase circuit, and an amplifier circuit coupled to the magnitude conditioning circuit and the phase conditioning circuit.

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract: A method of constructing, from a first array of entries, a second array of entries having a reduced number of entries compared with the first array is disclosed. According to one embodiment, the method comprises partitioning the first array into one or more groups of entries and then categorizing each group with a category categorizing relationships between entries of a respective group, or entries of a respective group and entries of another group. A compression code is then formed that contains a sequence of coded identifiers, each identifier identifying the category of a respective group. Finally, the second array is constructed to include selected entries from the first array. The selected entries depend on the category of each group and are arranged so as to be indexable by processing a first index into the first array and the compression code to derive a second index for retrieving an equivalent entry from the second array without decompressing the second array.

Abstract: A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.

Abstract: A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.

Abstract: A device, method, and computer readable medium are used in connection with providing an indication of zero crossings corresponding to a signal. The signal (113) is received. Noise is removed from the signal (103). In response to the signal with noise removed (115), pairs of points and a time value corresponding to each point are determined (105), wherein the points of each pair are proximate to a predetermined change in an amplitude of the signal. In response to the pairs and the corresponding time values (117), a zero crossing time is determined for each pair (107). A variation in the plurality of zero crossing times (119) is corrected (109). A signal (123) or indication representative of the corrected zero crossing times is output.

Abstract: A method and a device for processing instructions. The device includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. Whereas the second register group size information and the second register identification information define a second group of target registers associated with a second instruction.

Abstract: A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop.

Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.

Abstract: An audio communication unit comprises a receiver for receiving an audio signal, a sigma-delta modulator operably coupled to the receiver and arranged to modulate the received audio signal, and a class-D amplifier stage operably coupled to the sigma-delta modulator and arranged to amplify the modulated received audio signal. One or more feedback path(s) is/are arranged from an output of the class-D amplifier stage to the sigma-delta modulator. The provision of one or more feedback path(s) from the output of the class-D audio amplifier to the sigma-delta modulator facilitates smaller die size; higher power efficiency and power supply rejection ratio/intermodulation cancellation performance.

Abstract: A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits.

Abstract: A method of processing a code division multiple access signal comprises receiving a CDMA signal; processing the received CDMA signal with a CDMA detector; and extracting control channel information from the processed signal. The extracted control channel information is used to equalize a subsequent received CDMA signal, to make estimation of equalizer coefficients more reliable and increasing average data throughput.

Abstract: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

Abstract: A method is provided for transmitting data from a transmitting device (121) to a receiving device (125). The transmitting device transmits a first data frame (200) to a receiving device a first time (3100). Then it consecutively transmits the first data frame to the receiving device second through Nth times (3101-310N), each of second through Nth first data frame transmissions being made a first predetermined time period (350) after a respective previous first data frame transmission. After this, the transmitting device transmits a second data frame (200) to the receiving device a second predetermined time period (360) after the Nth first data frame transmission. In this method, N is an integer greater than 1, and the second predetermined time period is less than the first predetermined time period.

Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.