Abstract: A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205). The zirconium inhibits diffusion of silicon from the cap to the metal gate structure and gate dielectric. In one embodiment, the gate dielectric is a high K dielectric.

Abstract: A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The bit line driving circuitry further includes a first select input to receive a first select value, a second select input to receive a second select value, and an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.

Abstract: A radio frequency (“RF”) power amplifier circuit as described herein is configured to detect and measure an output load mismatch and to adjust the operating characteristics of the RF power amplifier to reduce output signal distortion. The circuit includes a directional RF signal coupler that obtains a coupled reflected RF signal that is indicative of the output load mismatch. The coupled reflected RF signal is processed to generate one or more bias control signals for the RF power amplifier. In operation, a mismatch condition will result in a measurable coupled reflected RF signal and a corresponding reduction in output power from the RF power amplifier. Ultimately, the output power control mechanism strives to maintain the RF power amplifier within a linear operating range.

Abstract: Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Abstract: An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic circuitry for detecting functional states of the memory, wherein the memory (a) supplies one or more programmed opcodes in response to detection of first functional states of the memory, and (b) supplies a hard coded opcode in response to detection of second functional states of the memory. The second functional states of the memory can include one or more of erase, write, self-test, and check-sum. The first functional states of the memory can include a functional state other than a second functional state.

Abstract: A noise blanker for use in a radio receiver includes an audio blanker (115) configured to mitigate impulse noise associated with a signal received by the radio receiver and a blanker controller (117) configured to selectively enable the audio blanker and further comprising at least a first blanker enabler and a second blanker enabler. The noise blanker controlled and corresponding method (500) can include a first noise detector, e.g., MPX noise detector (213), configured to provide a first signal when impulse noise is detected in a demodulated signal and a second noise detector, e.g., log RSSI noise detector (211), configured to provide a second signal when impulse noise is detected in a modulated signal, and a logic function (217) coupled to the first and second signals and configured to provide an enable signal to the noise blanker when the first signal or the second signal is provided. Note that in addition to or in lieu of either of the noise detectors, a switching enabler (215), responsive, e.g.

Abstract: A pulse width modulation circuit includes a first delay-locked loop (DLL) circuit and a second DLL circuit. The first DLL is coupled to a first multiplexer and has a first set of delay stages, wherein the first DLL circuit is configured to receive an input clock signal and, through the first multiplexer, produce a first stage delay signal associated with the first set of delay stages, wherein the first stage delay signal leads the input clock signal by a first duration.

Abstract: A flowmeter is provided that comprises a leadframe assembly (140) and a body (144) disposed at least partially around the leadframe assembly (140). The body (144) has a flow passage therethrough that comprises a first channel (178) having a first port (166), a second channel (180) having a second port (168), and a flow altering element (182) disposed within the second channel (180). First and second pressure sensors (174 and 176) are disposed within the body (144) and coupled to the leadframe assembly (140) for measuring a first pressure within the first channel (178) and a second pressure within the second channel (180), respectively. An integrated circuit (155), which is coupled to the leadframe assembly (140), to the first pressure sensor (174), and to the second pressure sensor (176), is configured to determine the rate of flow through the flow passage from the first pressure and the second pressure.

Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Abstract: A high-speed voltage regulating apparatus and a method for high-speed voltage regulation. The apparatus includes: (A) a regulator, adapted to provide a regulated voltage; (B) switching circuitry, connected to the regulator, adapted to either (i) connect the regulator to an output node or (ii) disconnect the regulator from the output node; whereas the output node is connected to a dynamic power consuming device and to a load capacitor; (C) control logic, connected to the regulator, adapted to receive at least an indication reflecting a voltage of the output node and to control the switching circuitry such that the regulator is disconnected from the output node to facilitate a decrease in the voltage of the output node.

Abstract: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

Abstract: A device and method for temperature compensation of an electronic device are disclosed. The device includes a temperature bias controller with a temperature sensor. A bias signal based upon a signal from the temperature sensor is provided to a first gate of a multiple fin gate field effect transistor (multigate FinFET) transistor of a functional block. A second gate of the multigate FinFET transistor receives a control signal to control its operation within the functional block. In this configuration the first gate of the multigate FinFET transistor can be used for temperature compensation while the second gate is used for functional operation of the transistor. Specific embodiments of the present disclosure will be better understood with respect to the figures.

Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

Abstract: A device and method for data image processing. The method includes writing, image data to a certain buffer by an image data provider; characterized by repeating steps of reading, by an image processor image data from a first entry of a certain buffer, processing the image data by the image processor, and writing processed image data to a second entry of the certain buffer; wherein the repeating ends when at least two memory pages of the certain buffer are read; wherein a distance between the first and second entries is smaller than a size of a page of the certain buffer and conveniently much smaller than the size of the page; wherein the second entry includes image data that was previously read by the image processor during the certain period; and preventing an image data provider and an image data retriever form accessing the certain buffer during the repetition.

Abstract: A gyro sensor configured to sense an angular rate about a rotational axis includes a drive mass configured to undergo oscillatory linear motion within a plane, and a sense mass configured to undergo an oscillatory motion out of the plane as a function of the angular rate. A link spring component connects the sense mass to the drive mass such that the sense mass is substantially decoupled from the drive mass with respect to the oscillatory linear motion of the drive mass, but is coupled to the drive mass with respect to the oscillatory motion out of the plane of the sense mass.

Abstract: A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24? of the second dopant type.

Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ? and/or lower loss tangent ? than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ? buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower ? buffer region reduces the parasitic loss in the encapsulation. Low ? and/or ? buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ? less than about 3.0 and/or ? less than about 0.005.

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.