Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.

Abstract: A method of multi-mode communications includes receiving signals from multiple sources at a plurality of sample buffers, referencing the plurality of sample buffers for a first source at one time and referencing the plurality of sample buffers for a second source at another time, and communicating data from the referenced plurality of sample buffers to a processing unit. The processing unit concurrently receives inputs from buffers in the plurality of sample buffers and outputs to other buffers in the plurality of sample buffers.

Abstract: A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.

Abstract: Methods have been provided for forming both wide and narrow trenches on a high-aspect ratio microelectromechanical (MEM) device on a substrate including a substrate layer (126), an active layer (128), and a first sacrificial layer (130) disposed at least partially therebetween. The method includes the steps of forming a first trench (154), a second trench (156), and a third trench (152) in the active layer (128), each trench (154, 156, 152) having an opening and sidewalls defining substantially equal first trench widths, depositing oxide and sacrificial layers thereover and removing the oxide and sacrificial layers to expose the third trench (152) and form a fourth trench (190) in the active layer (128) from the first and the second trench (154, 156), the fourth trench (190) having sidewalls defining a second trench width that is greater than the first trench width.

Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

Abstract: A differential capacitive sensor (50) includes a movable element (56) pivotable about a rotational axis (60). The movable element (56) includes first and second sections (94, 96). The first section (94) has an extended portion (98) distal from the rotational axis (60). A static layer (52) is spaced away from a first surface (104) of the moveable element (56), and includes a first actuation electrode (74), a first sensing electrode (64), and a third sensing electrode (66). A static layer (62) is spaced away from a second surface (106) of the moveable element (56) and includes a second actuation electrode (74), a second sensing electrode (70), and a fourth sensing electrode (72). The first and second electrodes (64, 70) oppose the first section (94), the third and fourth electrodes (66, 72) oppose the second section (96), and the first and second electrodes (68, 74) oppose the extended portion (98).

Abstract: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

Abstract: A BTSC encoder includes dual channel ADC, sync separator, audio processor, filtering device, and a composite audio signal generating device. The filtering device includes a first filter for providing a filtered L+R signal, and a second filter for providing at least one of: i) a filtered and combined pilot and modulated L?R signal and ii) separately filtered pilot and modulated L?R signals. The composite audio signal generating device is responsive to the filtered L+R signal, and at least one of i) the filtered and combined pilot and modulated L?R signal and ii) the separately filtered pilot and modulated L?R signals for generating and outputting a composite analog audio signal. In all embodiments, the modulated L?R signal is filtered via an anti-splatter filter.

Abstract: Method and apparatus are provided for linearized balanced signal mixing. A signal mixing circuit (10) for translating a radio frequency (RF) signal is provided comprising an input amplifier (12), a mixer network (14), and an output buffer amplifier (18). The input amplifier (12) is configured to produce an amplified RF signal and cancel an input third-order intermodulation (IM3) distortion in the amplified RF signal with a cross-coupled feedback amplifier (13). The mixer network (14) is configured to produce an intermediate frequency (IF) signal based on the amplified RF signal and a local oscillator signal. The output amplifier (18) is configured to buffer the IF signal and cancel an output IM3 distortion in the IF signal with a cross-coupled feedback amplifier (19). The input amplifier (12) and cross-coupled feedback amplifier (13) also serve as a bias current source for the mixer network (14), thus lowering the supply voltage required for the mixing circuit (10).

Abstract: An amplifier, tuner, and method of amplification are provided. The amplifier has a pair of transistors. Each transistor has a control terminal and an output terminal disposed between the transistor and a power supply input. A first network is connected between each power supply input and output terminal. The first network contains a first resistor and a first switch connected in parallel with the first resistor. A second network is connected between the transistors. The second network contains a first and second combination. Each of the first and second combinations contains a second resistor and a second switch connected in parallel with the second resistor. The first and second combinations are connected by a third switch.

Abstract: A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a given estimate to the number. The current estimate is updated based on this comparison and the inverse function of the current estimate is stored. The next estimate is an incremental change from the previous estimate and there is a corresponding incremental change in the inverse function from the current estimate to the next estimate. Rather than calculating the whole inverse function, which would typically require a multiplier, only the incremental change in the inverse function is provided simply. The incremental change in the inverse function is then added to the inverse function of the current estimate and compared to the number for determining the utility of the next estimate.

Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Abstract: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

Abstract: An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.

Abstract: A device is disclosed having a first Field Effect Transistor having a channel region controlled by a gate, a second Field Effect Transistor having a first channel region substantially controlled by a first gate, and a second channel region substantially controlled by a second gate. The gate of the first Field Effect Transistor and the first gate of the second Field Effect Transistor are coupled to a memory write line. The second gate of the second Field Effect Transistor receives a control signal from a memory bit cell.

Abstract: A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.

Abstract: A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.

Abstract: At least one adjustable gain analog amplifier (120, 124 and 128) in an analog line-up (102) amplifies by a gain an analog signal at an input of the analog line-up (102). The at least one adjustable gain analog amplifier (120, 124 and 128) is operable at one or more gains. At least one digital estimation device (134, 140 and 146) receives signal via an output (108) of the analog line-up (10) and provides a digital signal estimate representative of an analog signal at an input of a respective one of the at least one adjustable gain analog amplifier (120, 124 and 128) in the analog line-up (102). An AGC controller (152) monitors the digital signal estimate. The AGC controller (152) adjusts the gain of the at least one analog amplifier (120, 124 and 128). An RF receiver and an integrated circuit utilizing the novel features are also disclosed.

Abstract: In an immersion lithography method, the photoresist layer is provided with a shield layer to protect it from degradation caused by contact with the immersion liquid. The shield layer is transparent at the exposure wavelength and is substantially impervious to the immersion liquid. The shield layer can be formed of a material which can be removed using the same developer as is used to develop the photoresist layer after exposure.