Abstract: A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method includes, for each bit stream, sampling P data presented on a positive edge of a clock, sampling N data presented on a negative edge of the clock, and delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle. Delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle is selected to remove any skew and aligns the sampled P and N data between bit streams.

Abstract: A high-performance crystal oscillator providing effective bias resistors with low power consumption and minimal substrate surface area. In various embodiments of the invention, a switched-capacitor resistor is operably coupled to circuit components, such as an oscillation source, a current source, an input buffer, or an amplifier to provide a bias resistance.

Abstract: A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

Abstract: A radio frequency (RF) transceiver is provided. The RF transceiver comprises a transmit path comprising an output coupled to an RF antenna, a feedback path comprising an input coupled to the output of the transmit path, and a DC offset calibration module comprising a first input coupled to an output of the feedback path, a second input to receive a first signal and an output connected to an input of the transmit path. The DC offset calibration module is operable to determine a first direct current (DC) offset of a closed-loop path comprising the transmit path and the feedback path and determine a second DC offset based on the feedback path exclusive of the transmit path.

Abstract: An arrangement and method for Turbo processing iterative decoding in a radio receiver comprises receiving a block of data for decoding; decoding a whole block of data to produce a respective decoded output; dividing the received decoded whole block of data into a plurality of sub blocks; producing a determination of whether the decoded output of each of the sub blocks has substantially converged; storing said determination for each of the sub blocks; and further decoding over the whole block of data only sub blocks whose determinations do not indicate substantial convergence.

Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.

Abstract: A miniature vertically polarized multi-frequency antenna 10 is embedded in a substrate 11 and suitable for use within a wireless device. The antenna 10 includes a first lateral member 14 and a second lateral member 16, which is spaced from and parallel to the first lateral member 14. The antenna 10 has a wide tuning range due to multiple resonances provided by the lateral members 14, 16. The antenna 10 is shortened by reactive loading and by embedding the antenna in material having a high dielectric constant. Tuning circuits 30, 32 are coupled to respective ends of one of the lateral members 14, 16. The tuning circuits are located on a common plane with the lateral member to which they are connected. The tuning circuits 30, 32 electronically add reactance to the antenna to alter the frequency at which it resonates.

Abstract: A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharging a selected bitline to a first predetermined voltage in response to a first precharge signal. The current-to-voltage converter has a current input coupled to the selected bitline, and a voltage output. A latch circuit has a storage node coupled to the voltage output of the current-to-voltage converter. The second precharge circuit is for precharging the storage node of the latch circuit to a second predetermined voltage in response to a second precharge signal.

Abstract: A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.

Abstract: An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or a write cycle and not necessarily when the memory is in a special test mode. As errors are corrected, the error corrections are counted by an error counter (24) to create a count value. The count value is stored in the MRAM core itself and can later be retrieved and read during a test mode for an indication of how many bit corrections are required for the MRAM core over a period of time. The count value is stored by using an unused portion of a write memory cycle during a read operation.

Abstract: A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, the first node is electrically connected to ground, whereby a first divided voltage is generated at a first node of the latch.

Abstract: A method for determining polynomials to model circuit delay includes the step of determining one or more error areas in a characteristic map that exceed an error margin. Next, a current domain count is set to zero and selecting one error area of the one or more error areas is selected. A patch region that will contain the error area determined the patch region is then curve fitted and the current domain count is increased by one. The steps of repeating steps of selecting an error area, determine a patch, curve fitting within the patch, and increasing the domain count by one are repeated until there are no error area within the patch region.

Abstract: A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material (317).

Abstract: Apparatus and methods that reduce the amount of conducted/radiated emissions from a power switch (200) when a transistor (210) is switched OFF are disclosed. In addition, apparatus and methods that reduce the slew rate in a power switch when the power switch is switched off are disclosed. The apparatus comprises a transistor (210) including an inductive load (230) coupled to the transistor, a plurality of current sources (222, 224) coupled to the gate of the transistor, and a clamp (250) coupled to either the gate and the drain of the transistor, or to the gate and to ground depending on the location of the inductive load, wherein the clamp comprises a resistive element (260) to increase the voltage of the clamp when current flows through the clamp, and wherein the increased voltage causes the apparatus to include a different slew rate.

Abstract: A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.

Abstract: A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

Abstract: A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate, a buffer layer comprising at least one of silicide and germanide formed over the semiconductor substrate, and a crystalline semiconductor layer formed over the metallic buffer layer.

Abstract: A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.