Abstract: An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can be formed and substantially fill the trench. The insulating features help to reduce capacitive coupling between the heavily doped regions and the control gate electrode layer. In a particular embodiment, the insulating features are recessed from a top surface of a layer outside the trenches. The control gate electrode layer can form a substantially continuous electrical path along the lengths of the word lines. This particular embodiment substantially eliminates the formation of stringers or other residual etching artifacts from the control gate electrode layer within the array. A process can be performed to form the electronic device.

Abstract: Methods and apparatus are provided for an electronic device having an autonomous memory checker for runtime security assurance. The autonomous memory checker comprises a controller, a memory reference file coupled to the controller, and an authentication engine coupled to the controller. A check is performed during runtime operation of the electronic device. The autonomous memory checker generates runtime reference values corresponding to trusted information stored in memory. The runtime reference values are compared against memory reference values stored in the memory reference file. The memory reference values are generated from the trusted information stored in memory. An error signal is generated when the runtime reference values are not identical to the memory reference values thereby indicating that the trusted information has been modified.

Abstract: In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

Abstract: A receiver correlator structure for an ultra wide bandwidth communication system includes an antenna, a mixer, a bandpass filter, and a convertor. The receiver receives, via the antenna, an ultra wide bandwidth signal comprising a sequence of wavelets of particular shapes and positions, and transmits the received ultra wide bandwidth signal to the mixer. The mixer also receives and mixes with the received ultra wide bandwidth signal a local ultra wide bandwidth signal comprising a sequence of wavelets of particular shapes and positions correlated to the received ultra wide bandwidth signal. The bandpass filter removes the DC components from the mixed signal, and provides the resultant signal to the convertor. The receiver structure eliminates the local ultra wide bandwidth signal AC bias and DC bias terms and 1/f noise, yet detects long sequences of logical 1's and 0's, and allows operation with reduced bandwidth convertors.

Abstract: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.

Abstract: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.

Abstract: A digital clock generation circuit (200) and method of operation (400). A digital clock (202) produces an output (220) with a first frequency or a second frequency. A clock control circuit (204, 206) selectively sets the digital clock (202) to produce either the first frequency or the second frequency. An excess pulse counter (212) determines a number of pulses produced by the digital clock (202) at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit (230, 232, 212) removes, in response to the digital clock (202) changing from producing the second frequency to producing the first frequency, the number of pulses from the output (220) that were counted by the excess pulse counter (212).

Abstract: A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.

Abstract: A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low voltage circuit outputs a low drive voltage or ground voltage. The high voltage circuit outputs a high drive voltage or a high reference voltage, which is supplied to an RS latch circuit via a potential adjustment circuit at a level equal to an output potential at the low voltage circuit. The RS latch circuit uses the output of the potential adjustment circuit when the input voltage shifts to a high level and uses the output of the low voltage circuit when the input voltage shifts to a low level.

Abstract: A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes determining whether each cell in the portion of the NVM passes a first margin level, if not determining which one of a set of lower margin levels than the first margin level each cell in the portion of the NVM passes. The method further includes modifying at least one of the set of parameters associated with a subsequent program/erase operation for the portion of the NVM based on the determined one of the set of lower margin levels.

Abstract: A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.

Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.

Abstract: A semiconductor storage cell includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.

Abstract: An ultra-wide band (UWB) waveform generator and encoder are provided. The encoder multiplies each data bit by an n-bit identifying code to create a stream of bits corresponding to each data bit, i.e., an original codeword. The original codeword is passed to the UWB waveform generator for generation of a UWB waveform comprised of shaped wavelets that can be transmitted via an antenna. The UWB waveform generator may use a two-stage differential mixer. A first stage combines pulses from a pulse generator with a first derivative codeword derived from the original codeword. The wavelet output from the first stage is input to a second differential mixer along with a second derivative codeword also derived from the original codeword and orthogonal to the first derivative codeword. The wavelet output from the second mixer represents an inversion of the original codeword, and is passed to an inverting amplifier before being transmitted.

Abstract: A digital clock frequency multiplier (100) for increasing an input frequency of an input clock signal includes a generator (102) that receives the input clock signal and a high frequency digital signal. The generator (102) divides a count (Nhf) of a number of cycles of the high frequency digital signal in one period of the input clock signal by a predetermined multiplication factor (MF) for generating an output clock signal. The output clock signal has a predetermined output frequency.

Abstract: A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (<0.3 ?m) power MOSFET using existing 0.13 ?m process flow without additional masks and processing steps.

Abstract: A multi-band high gain mixer and quadrature signal generator allows a receiver system to receive signals at multiple frequency bands without requiring significant hardware duplication. A single mixer directly receives any of three communication frequency bands such as Universal Mobile Telecommunication System (UMTS), Personal Communication Services (PCS), Digital Communication System (DCS), and Japan and US W-CDMA 800 bands without amplification. A Serial-Parallel Interface selectably forwards RF signals within the receiver's frequency channels to the mixer for demodulation into in-phase (I) and quadrature (Q) signals at a common IF output from the multi-mode receiver. Significant power and cost advantages are attained by elimination of duplicate mixers and amplifier stages.