Abstract: A method is provided for performing a clear channel assessment in a local device. The local device receives signal energy in a wireless channel and splits the received signal energy into a real portion and an imaginary portion. It determines a real portion of a squared signal energy by subtracting a squared imaginary portion of the signal energy from a squared real portion of the signal energy, and determines an imaginary portion of the squared signal energy by calculating twice the product of the real and imaginary portions of the signal energy. It can perform a signal detection function on the real and imaginary portions of the squared signal energy to produce a clear channel assessment signal that indicates whether a set signal type is present in the wireless channel. This clear channel assessment signal can be used to determine whether the local device should remain in a low-power mode.

Abstract: An accumulated current counter (11) includes a sense resistor (30) configured for being coupled in series between an electronic circuit (13) and a power source (12). The sense resistor is further for use in sensing a voltage (VIN(i)) across the sense resistor as a function of a current (Ibatt) provided via the power source. An incremental counter (16) is coupled to the sense resistor for incrementally counting an amount of current, corresponding to an average value of charge Q, going (i) into or (ii) out of the power source. A register (63) accumulates a representation of the incrementally counted current. In one embodiment, the representation of incrementally counted current corresponds to a remaining power source life in hours and minutes.

Abstract: An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

Abstract: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

Abstract: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.

Abstract: A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a first side of the gate electrode in an upper surface of the substrate and a second source/drain region adjacent a second side of the gate electrode is below a lower surface of the recess. Etching the exposed portion of the substrate may be done so as to form a rounded corner at the junction of the recess sidewall and the recess lower surface. The silicon germanium film formation is preferably epitaxial. An epitaxial silicon film may be formed adjacent the silicon germanium film.

Abstract: An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

Abstract: A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.

Abstract: A wide linear range peak detector including first and second peak detectors and a compensation circuit. The first peak detector receives an input signal and has an output providing a first peak signal approximation which approximates a peak level of the input signal. The first peak signal approximation includes a non-linear portion which is a function of the peak level of the input signal. The second peak detector also receives the input signal and has an output providing a second peak signal approximation. The compensation circuit uses the second peak signal approximation to provide a compensation signal which compensates the non-linear portion of the first peak signal approximation. In particular, the second peak signal is used to generate the compensation signal to approximate and cancel the non-linear portion.

Abstract: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series.

Abstract: An antenna (100) is provided. The antenna includes: a first ground element (105); a first driven element (110) formed from a planar piece of conductive material, the first driven element being configured to transmit and receive wireless signals, the first driven element including a physical slot (130); a conductive line (135) formed in the physical slot such that the conductive line is separated from the first driven element by a gap (G) filled with non-conductive material, the conductive line having a line impedance that is a function of an effective line width of the conductive line, and an effective gap width of a gap between the conductive line and the first driven element; and a signal line (120) configured to send and receive signals to and from the conductive line.

Abstract: A method is provided for operating a wireless device. In this method, a first operation is performed on a wireless signal using a first group of wavelets arranged according to a first analog code word format (720). A second operation is then performed on the wireless signal using a second group of wavelets arranged according to a second analog code word format (740). The first code word format can be different in content and in size from the second code word format. By choosing different properties for each analog code word format, the device can optimize the performance of each operation. These operations can be performed in receiving process (800) or a transmission process (900).

Abstract: A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The active hole removal is faster than passively allowing holes to be removed, which can take milliseconds. The active hole removal can be achieved by reducing the drain voltage to a negative voltage and reducing the gate voltage as well. This results in directly withdrawing the holes from the floating body to the drain. Alternatively, reducing the drain voltage while maintaining current flow stops impact ionization while sub channel current collects the holes. Further alternatively, applying a negative gate voltage causes electrons generated by band to band tunneling and impact ionization near the drain to recombine with holes.

Abstract: A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.

Abstract: A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.

Abstract: A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

Abstract: A dyadic spatial down sampling filter having tap values configured according to a Kaiser window function a beta factor of approximately 2.5, having approximately 1.5 side lobes, and having a down sampling ratio of approximately 1.9. The dyadic spatial down sampling filter may have tap values [?1, 17, 32, 17, ?1]/64. A dyadic spatial up sampling filter having tap values configured according to a Kaiser window function having a beta factor of approximately 1.5, having approximately 2 side lobes, and having an up sampling ratio of approximately 2. The dyadic spatial up sampling filter may have tap values [?5.44, 0, 20.71, 33.46, 20.71, 0, ?5.44]/64.0, or tap values [?5, 0, 21, 32, 21, 0, ?5]/64, or tap values [?5, 21, 21, ?5]/32.

Abstract: A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produce a result vector having the number of vector elements. Each vector element of the result vector is associated with an arithmetic logic cell that has a first input that can receive any vector element from the first vector and a second input that can receive any vector element from the second vector. Accordingly each vector element of the result vector is a function of any two individual vector elements of the operand vectors. By applying the operand vector elements to the appropriate arithmetic logic cells, and by selecting the appropriate arithmetic operation, complex vector operations can be performed efficiently.

Abstract: Methods and apparatus are provided for gain and phase compensation in a radio frequency (RF) transmitter (108). The RF transmitter (108) has at least one power amplifier (PA) (205) for providing a transmitted signal having a signal power therefrom. An RF power detector (208) is coupled to the at least one PA (205) for detecting the signal power of the transmitted signal and an analog to digital (A/D) converter (210) is coupled to the RF power detector (208). A hysteresis unit (214) is coupled to the A/D converter (210) for generating a pulse (222) in response to a power threshold being crossed and a load switch control unit (218, 232) is coupled to the hysteresis unit and the at least one power amplifier for providing gain and phase compensation in response to the pulse.