Abstract: A timing and carrier error detector module (127) of a communication receiver (111). The timing and carrier error detector module uses phase information of a correlated signal (e.g. a Barker de-spread signal) to generate a timing signal and carrier error signal. In one example, the phase information includes a phase error signal of the correlated signal. In one example, the timing and carrier error detector module calculates an indication of the variance of the phase error signal for a plurality of sample positions over a plurality of Barker symbol intervals. The timing signal is based upon the sample position having a minimum indication of a variance.

Abstract: A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.

Abstract: A method for packaging a semiconductor device includes forming through holes (12) in a base substrate (10) and depositing a conductive material (14) on a first side (16) of the base substrate (10) to form a conductive layer (18) such that the conductive material (14) fills the through holes (12). The conductive layer (18) is patterned and etched to form interconnect traces and pads (22). Conductive supports (24) are formed on the pads (22) such that the conductive supports (24) extend through respective ones of the through holes (12).

Abstract: Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608).

Abstract: A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.

Abstract: An identification tag is provided in which radio frequency (RF) circuitry and ultrawide bandwidth (UWB) circuitry are both provided on the same tag, along with some UWB-RF interface circuitry. The RF circuitry is used to detect when the identification tag must be accessed, and is used to connect the UWB circuitry with a power supply. The UWB circuitry then performs the necessary communication functions with a distant device and the power supply is again disconnected. In this way the power supply is only accessed when the UWB circuitry is needed and it's usable lifetime can be maximized.

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.

Abstract: A device having a temperature sensor device is disclosed. The temperature sensor device includes a complementary to absolute temperature (CTAT) module and a reference module. Both the temperature sensor and the reference voltage module provide signals, that vary in a complementary relationship with the variation in temperature. While the signals can be voltages or currents, for purposes of discussion the signals are discussed in terms of voltages herein. The reference module provides a signal that has a relatively small variation with temperature as compared to the variation in a signal provided by the CTAT module. The signals are provided to a comparator, which provides a temperature control signal based on a comparison of the input signals.

Abstract: A method and system for decoding a received data stream are disclosed. The appropriate time interval to decode the received data stream is derived from the data stream itself. A header of the data stream is analyzed to determine two sets of time ranges, each set of time ranges corresponding to a set of possible data transmission intervals. A preamble of the header contains timing information for development of a first set of time ranges to decode a synchronization word of the header. The synchronization word contains both data information and timing information to develop the second set of time ranges. The data information included in the header is used validate the data stream for the receiving device. The second set of time ranges is used to decode a data payload portion of the data stream.

Abstract: Automated software loading into a battery-less mobile phone is accomplished through attachment of a special non-standard USB On-The-Go cable to a serial connector of the mobile phone, thereby delivering power supply and unique signals for placing the phone in a special mode of operation used for production or distribution. In operation, when a unique non-standard voltage is asserted on the identification (ID) pin of the USB connector interface, it is detected by special circuitry in the serial connector. The circuitry then enables power supply to the battery-less phone and generates a turn-on signal directing the mobile phone to automatically power-on and enter into a particular state of operation, for example a test or software loading mode. Because this process is automatic, the efficiency of software loading or testing during production or distribution of the mobile device is improved.

Abstract: A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive element and substantially lattice matched to the semiconductor material.

Abstract: A method for programming a non-volatile memory (NVM) cell includes applying an increasing voltage to the current electrode that is used as a source during a read. The initial programming source voltage results in a relatively small number of electrons being injected into the storage layer. Because of the relatively low initial voltage level, the vertical field across the gate dielectric is reduced. The subsequent elevation of the source voltage does not raise the vertical field significantly due to the electrons in the storage layer establishing a field that reduces the vertical field. With less damage to the gate dielectric during programming, the endurance of the NVM cell is improved.

Abstract: A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate electrode, wherein the second gate electrode comprises silicon. Nanoclusters are present in the first gate electrode. A peripheral transistor area is formed devoid of nanoclusters.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.

Abstract: Power supply apparatus with overload protection comprising a switch responsive to an input signal for switching between an ON-state for supplying current from a source of power to a load and an OFF-state for interrupting the supply of current to the load, and protection means responsive to an overload condition to switch the switch to the OFF-state. The protection means is responsive to a first overload condition during an initial phase after the switch switches to the ON-state so as to switch the switch back to the OFF-state and maintain the switch in the OFF-state. The protection means is subsequently responsive to a second overload condition if the first overload condition is not detected during the initial phase so as to switch the switch to the OFF-state and subsequently switch the switch back to the ON-state after an interval of time.

Abstract: Keypad apparatus for registering signals corresponding to data that a user enters by pressure on keys of an array in a surface extending in two dimensions. The elements of first and second sets of impedance elements (R) are connected in series through respective interconnections and a signal processor applies first and second reference signals across the first and second sets of impedance elements respectively. User pressure on the keys makes or breaks connections through corresponding contact elements between a respective pair of the interconnections, one from the first set of impedance elements and one from the second set of impedance elements, so as to generate first and second output signals (PX1, PY1) that together are a corresponding combination of the first and second reference signals that is unique to the actuated key elements.

Abstract: An overcurrent protection circuit and DC power supply that are subtly affected by process and device differences, have small input and output voltage drops, and set maximum and short-circuit current values. In a normal operation mode, a first operational amplifier and an output transistor keep the output voltage constant. In a current limiting mode, when a large current is input to an input terminal due to transient response, a second detection transistor and a third operational amplifier control a second control transistor to keep the maximum current of the output transistor constant. When voltage decreases during a foldback mode, a first detection transistor and a second operational amplifier control a first control transistor to control short-circuit current of the output transistor. A second operational amplifier decreases output current in accordance with the output voltage with a current source that maintains constant mutual conductance.

Abstract: Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack (110) including metal pads (112) and a substrate (116). An adhesion/plating layer (115) is formed on the substrate (116). A layer of gold (118) is plated on the adhesion/plating layer (115). The layer of gold is etched in a street area (124) to expose edge portions (128) of the layer of gold (118) and the adhesion/plating layer (115). A layer of barrier metal (130) is deposited to form an edge seal (129) about the exposed edge portions (128). The edge seal (129) prevents the leaching of gold from back metal layers (118) into the solder (162) when the wafer stack (110) is soldered to a leadframe (162).