Abstract: A deglitch circuit capable of removing noise with low power consumption. Voltage is input to a first inverter, connected to a power supply line via a first current source and grounded via a second current source. The first inverter is grounded via a capacitor and connected to first and second transistors. The gate terminals of these transistors receive a second control voltage, which is lower than the power supply voltage, and a first control voltage, which is higher than the ground level. The second transistor is connected to the ground line via a fourth current source. First voltage is supplied to a first input terminal of the latch circuit via a second inverter. The first transistor is connected to the power supply line via a third current source. Second voltage is supplied to a second input terminal of the latch circuit via the second inverter.

Abstract: Multi-chip semiconductor device assemblies and methods for fabricating such assemblies are provided. An exemplary assembly comprises a first chip having a first surface and comprising a plurality of conductive pads disposed at the first surface and a plurality of circuits. Each of the pads is electrically coupled to one of the circuits. A second chip having a second surface is disposed adjacent to the first surface of the first chip. The second chip comprises a plurality of bonding members disposed at the second surface. Each of the bonding members is connected to a corresponding pad. The second chip is electrically coupled to at least one of the circuits via a corresponding pad and a corresponding bonding member. The second chip comprises a first and a second portion. The first portion overlies at least a portion of the first chip and the second portion extends beyond the first chip.

Abstract: A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain contacts away from the fins as much as reasonably possible. The gate contacts extend upward from the top surface of the elevated semiconductor portion. The gate also extends upward from the top surface of the elevated semiconductor portion. The contacts are located between the fins where the gate is below the height of the elevated semiconductor portion so the contacts are as far as reasonably possible from the gate, thereby reducing gate to drain capacitance and providing additional assistance to alignment tolerance.

Abstract: An apparatus and method are provided for tracking the poles of an integrated RC filter as well as the absolute value of a current source. A single tracking oscillator contains integrated elements such as a programmable resistor and fixed capacitor or a programmable capacitor and fixed resistor. The programmable element is programmed such that a particular response from the RC filter is achieved and the word used to program the programmable element is then supplied to other integrated RC filters having components that were fabricated at the same time as the RC filter in the tracking oscillator. A highly accurate external capacitor or resistor is supplied to determinate the absolute value of the programming element, which is used to program one or more current sources containing the programmable resistor.

Abstract: A detector or a modulator for converting between optical and radio frequency signals comprising an optical guide (11 to 14) for propagating two optical signal components having frequencies that differ by an amount corresponding to a radio frequency and a microstrip radio signal guide (15, 16) for propagating a radio signal at the radio frequency, the microstrip radio signal guide being in travelling-wave coupling with an interaction one (14) of the optical guide comprising material in which interaction between the optical signal components and the radio signal occur. The microstrip radio signal guide element (15, 16) comprises an electrically conductive strip (15) juxtaposed with and extending along the interaction zone (14) on one side thereof and an electrically conductive ground plane (16) juxtaposed with and extending along the interaction zone (14) on an opposite side thereof.

Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).

Abstract: A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time interval between the data transitions is measured, and a logic value of a data bit encoded in the data stream is decoded based on the measured time interval. By decoding the data stream based on the time intervals between data transitions, the number of decoding errors due to timing changes in the data stream (such as changes due to drift or jitter in the data stream) is reduced.

Abstract: An electronic device can include a substrate (12) having a primary surface (14), a second surface (16, 22) opposite the primary surface (14), and an electrode (50). In one embodiment, the electrode (50) can lie adjacent to the second surface (22) and include, a barrier layer (54) lying between a conductive layer (56) and a metal-containing layer (52), wherein the metal-containing layer (52) includes a first metallic element and not a second metal element, and the barrier layer (54) includes the second metal element and not the first metallic element. In another embodiment, an adhesion layer (52) and a conductive layer (56) can each include a metallic element, and lie immediately adjacent to a barrier layer (54). In still another embodiment, a process for forming an electronic device can include removing a portion of the substrate (12) opposite a primary surface (14).

Abstract: A system (100) for reconfiguring a remote device (102) (e.g., a client device) that includes at least one processor (200) and reconfigurable logic (202) that is operatively coupled to the processor (200), employs for example, a network element that serves as a remote profile server (104) for the remote device (102). The remote device (102) includes an application profiler (206) that produces application runtime profile statistic information (120) during runtime of an application running on at least one processor (200) of the device. The remote profile server (104) includes a profile analyzer (130) that analyzes the received application runtime profile statistic information (120) to determine suitable reconfigurable logic configuration information (122) and corresponding application patch information (124) for the remote device (102).

Abstract: A method for etching a dielectric film is provided herein. In accordance with the method, a device (201) is provided which comprises a first chamber (203) equipped with a first gas supply (209) and a second chamber (205) equipped with a second gas supply (215), wherein the second chamber is in communication with the first chamber by way of an acceleration grid (211) having a variable potential. The gas flow into the plasma chamber is oscillated between a first state in which the gas flow into the first chamber has the composition f11 and the gas flow into the second chamber has the composition f21, and a second state in which the gas flow into the first chamber has the composition f12 and the gas flow into the second chamber has the composition f22.

Abstract: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage.

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract: A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a current from the bit cell, representative of a logic value, to the reference current. By basing the reference current on both a fixed and a trimmable current source, the reference device can be trimmed to compensate for process and operating characteristics of the device, while maintaining a minimum reference current in the event of a disturb mechanism that results in loss of the current provided by the trimmable current source.

Abstract: A frequency source having a fast start-up time and low noise in steady state is presented. The frequency source includes an oscillator and a hybrid automatic gain control (AGC) loop that switches between an analog AGC loop at oscillator start up and a digital AGC loop at steady state operation. The analog AGC loop includes a peak detector connected to the oscillator and an error integrator integrating the difference between the peak detector output and a reference voltage. The digital AGC loop includes a comparator comparing the peak detector output and high/low reference voltages, an oscillator counter providing a timer signal, a digital-to-analog converter (DAC) supplied with a digital word, and a low pass filter between the DAC and the oscillator. The timer signal causes a multiplexer to select either the analog AGC loop or the digital AGC loop.

Abstract: A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a first die section (210), a second die section (212) adjacent the first die section (210), and a strip (216) connecting the first die section (210) and the second die section (212), removing material from portions of the non-active surface of the substrate (206) on which the backing material (104) is not deposited to thereby partially separate the substrate (200) into a first die (236) and a second die (238) connected to one another by the strip (254) of the deposited backing material, and breaking the strip connector (254) to separate the first die (236) from the second die (238).

Abstract: A multiple step process is performed at a local wireless network to limit interference between the local wireless network and a remote wireless network. Initially, a set of code words is chosen for the local wireless network to encode data with that have good cross correlation properties. If these initial code words are not adequate to prevent interference, then the local wireless network will adjust its transmission parameters by either shifting the transmission phase of its signals or by changing the code words it uses. If altering the transmission parameters does not alleviate the interference problem, then the local wireless network attempts to locate the interfering remote network and merge with it. If the merger is not possible or is unsuccessful, then the interference limiting process fails.

Abstract: Methods and apparatus are provided for testing a magnetoresistive random access memory (MRAM). A magnetoresistive tunnel junction (MTJ) has a first terminal, a second terminal, and a third terminal. A source measuring unit is coupled to a first terminal of a MTJ to provide DC biasing. A current preamp has an input coupled to a third terminal of the MTJ for receiving current corresponding to a resistance of the MTJ. A pulse generator is AC coupled to the MTJ for programming the MTJ. A method of insitu testing a MTJ in a manufacturing environment uses a probe station coupled to the MTJ. A probe station couples to the MTJ. The MTJ is DC biased for generating a current corresponding to the logic level stored in the MTJ. A pulse for programming the MTJ is AC coupled to the MTJ.

Abstract: Multiple burst memory access handling protocols may be implemented at the hardware level or evaluated and selected during design of the hardware. The appropriate burst protocol may be selectable based on burst characteristics such as burst types and the identity of the current bus master. This allows, for example, the ability for a slave to support multiple error protocols in a multi-master system on a chip (SoC), or to design slaves capable of interfacing with a variety of masters which use different burst handling protocols. Inputs such as a programmable control register or configuration pins or variables may be provided to as part of the slave or slave interface block (e.g., a memory controller) to facilitate the implementation of alternate burst protocols. When a burst request is received from a master, a burst characteristic corresponding to the requested burst is determined and one of a plurality of burst error protocols is selected based on the burst characteristic.

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130).

Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat??sat)?(Hsw+?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.