Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein from a top view, the conductive stud (34) lies substantially completely within the opening (112, 24).

Abstract: A CMOS class A/B output stage provides the advantages of high speed operation, low supply voltage requirements, and low quiescent current draw, resulting from the use of subthreshold biasing of the output driver transistors. The architecture of the output stage makes it particularly suitable for use in operational amplifiers in power demanding applications, such as portable instruments, smoke detectors, sensors, or the like.

Abstract: Local oscillator apparatus comprising communication signal terminals for a communication signal, especially in a receiver or a transmitter, and a controlled frequency oscillator for producing a local oscillator signal. The local oscillator also includes a reference frequency generator and a feedback loop for selecting and adjusting the frequency of the local oscillator signal relative to the frequency of said reference frequency signal. A first frequency divider divides the frequency of the local oscillator signal by a first division factor to produce a conversion signal, where the frequency of said conversion signal is at least approximately equal to the frequency of the communication signal, and conversion means responsive to the conversion signal converts between said communication signal and base-band signal.

Abstract: A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134).

Abstract: A transceiver 400 is provided in an ultrawide bandwidth device, which includes an antenna 110, a transmitter circuit 145, and a receiver circuit 165. A transmitter amplifier 440 is provided between the antenna 110 and the transmitter circuit 145, and is configured to have an operational transmitter output impedance when the transceiver 400 is in a transmit mode and an isolation transmitter output impedance when the transceiver 400 is in a receive mode. A receiver amplifier 460 is provided between the antenna 110 and the receiver circuit 165, and is configured to have an operational receiver input impedance when the transceiver 400 is in a receive mode and an isolation receiver input impedance when the transceiver 400 is in a transmit mode. The isolation transmitter output impedance is greater than the operational receiver input impedance, and the isolation receiver input impedance is greater than the operational transmitter output impedance.

Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array.

Abstract: A system timer controls the timing at which a mobile communication device communicates with a base station. The system timer includes a sequencer that executes a set of instructions stored in a sequencer RAM thereby causing a set of control signals to be supplied to a set of components residing in the mobile communication device including, a set of RF hardware devices, a microprocessor and a digital signal processor. The microprocessor or the digital signal processor may alter the order in which the instructions are executed by the sequencer thereby allowing the mobile communication device to communicate in a dynamic multi-slot communication environment. The system timer may include a timebase counter used to synchronize the timing of the mobile communication device with the timing of the base station. A value stored in the timebase counter is incremented at a predefined rate and the value stored in the timebase counter wraps to zero upon reaching a predefined value.

Abstract: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.

Abstract: A method of forming a microelectronic device (300) including the steps of forming a sensor component (100) and a capping component (200). The sensor component (100) includes a sensor structure (150, 152) and a conductive trace (160, 162) formed on a first SOI semiconductor wafer (110). The capping component (200) includes a plurality of capping layers (230, 232) formed on a second SOI semiconductor wafer (210). During fabrication the capping component (200) is bonded to the sensor component (100) prior to fabrication of a through hole (260) in the capping component (200). Subsequent to bonding the two components together, wafer thinning removes a handle layer (112) of the first SOI semiconductor wafer (110) and a handle layer (212) of the second SOI semiconductor wafer (210).

Abstract: A method and apparatus are provided for operating a feedback network (300, 400). The method and apparatus operate to combine (240) a feedback signal (IF) and an incoming signal (VIN) to generate an adjusted signal (IADJ) at an input node of an amplifier element (110); amplifying the amplifier input signal in the amplifier element to produce an amplifier output signal (VOUT) at an output node of the amplifier element; processing the amplifier output signal according to a feedback operation (230) to generate the feedback signal (IF); and providing an assist current (350, 450, IASSIST) to the output node of the amplifier element, separate from an output current provided by the amplifier element.

Abstract: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.

Abstract: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).

Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.

Abstract: Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an exemplary embodiment, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip test module (e.g. a built-in self-test (BIST) module) contained within the semiconductor device provides an internal testing signal for the system logic. Control logic selectively provides appropriate input testing signals to the boundary shift registers and receives and processes appropriate output signals from the boundary shift registers in each testing mode. Using the various control techniques, a common set of boundary scan registers may be used to implement, for example, an IEEE 1149.1 interface, a BIST isolation wrapper scan chain, a BIST-mode input/output control, or the like.

Abstract: Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 ?, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.

Abstract: A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.