Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

Abstract: In the field of battery charging for electronic devices, it is known to employ a number of measures to avoid excessive power dissipation by a pass device in a charging system. However, many of these measures are either incompatible with linear charging regimes or add cost to the adapter and/or charging system. The present invention provides a power dissipation measurement circuit for controlling a control device that acts in series with another, but maximum current limiting, control device to control drive current to the pass device so as to limit the power dissipated by the pass device to a maximum threshold value.

Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

Abstract: A method is provided for adjusting timing alignment in which a receiver generates a plurality of imbalanced correction codes (1310), and square waves both having the same frequency. The receiver mixes the imbalanced correction codes with the square waves to create a mixed signal (1320), and integrates the mixed signal over a correction code period to generate a signal power value (1330). The receiver adjusts a phase of the square wave in a first direction when the signal power value satisfies a first criterion (1340, 1350), and in a second direction when the signal power value satisfies a second criterion (1340, 1360). Each imbalanced correction code is symmetrical. And a total integrated value of one of the imbalanced correction codes over the correction code period is either above a first threshold, or below a second threshold, the first threshold being greater than or equal to the second threshold.

Abstract: Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).

Abstract: An integrated circuit has an internal oscillator circuit for being connected to an external frequency source such as a crystal or a ceramic resonator. The internal oscillator circuit has an inverting amplifier across the frequency source terminals to establish an oscillation there. One terminal of the frequency source is coupled to one input of the comparator and to a second input of the comparator through a low pass filter. Coupling the output of the low pass filter to the second input of the comparator is for preventing a DC offset from developing between the two inputs of the comparator. The other terminal of the frequency source is coupled to the second input of the comparator through a high pass filter. The high pass filter provides the comparator with a larger voltage differential to increase noise margin. Noise margin is further improved by allowing an increase in hysteresis in the comparator.

Abstract: A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer on the polysilicon gate and to re-expose the previously exposed portion of the metal layer. The re-exposed metal layer is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer. Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate but for the protection provided by the sidewall spacer. After the re-exposed metal has been removed, a transistor is formed in which the metal layer sets the work function of the gate of the transistor.

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.

Abstract: A process for deriving a power transfer function of a circuit. The power transfer function can be used to represent the real time power consumption of a circuit based on the status of the inputs. In one embodiment, the power transfer function is derived from frequency domain analysis of signals applied to the inputs of a circuit during tests of the circuit. In one embodiment, the inputs of the circuit are grouped in groups based on a commonality of power consumption of the signals. The inputs may be grouped by clustering squared coherencies associated with the inputs. The transfer function may be implemented in a power monitoring circuit having inputs coupled to the inputs of the circuit to provide a real time estimation of power consumption of the circuit.

Abstract: A method for forming a portion of a semiconductor device includes: patterning gate stack layers overlying a substrate into a gate stack; implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the gate stack; oxidizing the gate stack at first oxidation conditions to form an oxidation layer on sidewalls of the gate stack; and oxidizing the gate stack at second oxidation conditions to form further oxidation of the oxidation layer on sidewalls of the gate stack. The second oxidation conditions are different from the first oxidation conditions.

Abstract: An integrated circuit package (50) is provided which comprises a substrate (20), an integrated circuit (12) mounted on the substrate, and a compressive, thermally conductive interposer (52) mounted on the integrated circuit.

Abstract: A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.

Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.

Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).

Abstract: A method for forming a semiconductor device is provided. The method includes forming a n-type well region. The method further includes forming a gate corresponding to the semiconductor device on top of the n-type well region. The method further includes forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant. The method further includes doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region. The method further includes forming a source and a drain corresponding to the semiconductor device.

Abstract: A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance is divided by sum of the ground capacitance and the coupling capacitance to compute a scale factor. The effective capacitance is then scaled by the scale factor to determine a delay noise induced load. Finally, the timing paths are optimized incrementally by using the delay noise induced load, the resistance, and the delay information.

Abstract: A discharge device and DC power supply system for preventing erroneous operation of a series regulator. The discharge circuit includes a voltage comparison circuit for comparing input power supply voltage and output power supply voltage of the series regulator. The voltage comparison circuit includes first and second transistors. The collector terminal of the second transistor is connected to the drain terminal of a fourth transistor and to the gate terminal of a fifth transistor. The fifth transistor has a drain terminal, which is connected to the output terminal of the series regulator, and a source terminal, which is grounded. Third and fourth transistors operate when the input power supply voltage is greater than the activation voltage. The drain terminal of the fourth transistor is grounded via a resistor, and the voltage of the fourth transistor is supplied to the gate terminal of the fifth transistor.

Abstract: A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.

Abstract: A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time interval between the data transitions is measured, and a logic value of a data bit encoded in the data stream is decoded based on the measured time interval. By decoding the data stream based on the time intervals between data transitions, the number of decoding errors due to timing changes in the data stream (such as changes due to drift or jitter in the data stream) is reduced.