Abstract: An array of photosensitive sensors each has a storage element to store a pixel value. A repeating fixed pattern noise correction module may be coupled to the photosensitive sensors to correct a repeating fixed noise pattern associated with the stored pixel values. In addition, a non-repeating fixed pattern noise hardware correction module may be coupled to the image sensor to correct a non-repeating fixed pattern noise associated with the pixel values stored in the plurality of elements. In a specific embodiment, one or both of the repeating fixed pattern noise correction module and the non-repeating fixed pattern noise hardware correction module are integrated onto a common substrate with the photosensitive sensors, and can comprise tables to identify specific fixed pattern noise locations.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form atop electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Abstract: A method, computer program product, and data processing system for determining test sequences' coverage of events in testing a semiconductor design are disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the design under test are transmitted to a “backend” computer in the form of an ordered dictionary of events and bitmap and/or countmap data structures. A “bitmap” data structure encodes Boolean information regarding whether or not a given event was covered by a particular test sequence. A “countmap” data structure includes frequency information indicating how many times a given event was triggered by a particular test sequence. The backend computer combines results from each test sequence in a cumulative fashion to measure the overall coverage of the set of test sequences.

Abstract: A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The bit line driving circuitry further includes a first select input to receive a first select value, a second select input to receive a second select value, and an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.

Abstract: A bus control system that reduces power consumption with a relatively simple structure. Load input signals are respectively provided to input capture registers. A free running counter provides each input capture register with a counter signal through a timer bus. A latch circuit is arranged in the timer bus. Capture conditions of each load input signal is input to an OR circuit connected to the latch circuit. When the capture conditions of at least one load input signal are satisfied, the latch circuit provides each input capture register with a counter signal.

Abstract: A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.

Abstract: A method (1200) is provided for allowing delayed acknowledgement in a local wireless transceiver. In this method the local transceiver (324) receives n data frames (1000) from a remote wireless transceiver (322), each data frame (1000) including a set of acknowledgement policy bits, which indicate a desired acknowledgement policy for the respective data frame (1000). The first (n—1) data frames (811-814) indicate an acknowledgement policy of delayed acknowledgement with no acknowledgement requested, while the final data frame (815) indicates an acknowledgement policy of delayed acknowledgement with acknowledgement requested. In response to the acknowledgement policy of the last data frame (815), the local transceiver (324) sends a delayed acknowledgement response frame (1135) to the remote wireless transceiver (322). This delayed acknowledgement response frame (1135) includes frame identifiers for the first (n?1) data frames (811-814), but does not include a frame identifier for the last data frame (815).

Abstract: A radio frequency (“RF”) circuit configured in accordance with an embodiment of the invention is fabricated on a substrate using integrated passive device (“IPD”) process technology. The RF circuit includes at least one RF signal line section and an integrated RF coupler located proximate to the RF signal line section. The integrated RF coupler, its output and grounding contact pads, and its matching network are fabricated on the same substrate using the same IPD process technology. The integrated RF coupler provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit.

Abstract: A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

Abstract: The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

Abstract: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer (44) over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (52). By forming the transition layer (32) with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer (32) is constructed having a lower region (e.g., 31, 33) with a polycrystalline structure and an upper region (e.g., 37, 39) with an amorphous structure that blocks silicon diffusion.

Abstract: A method of testing critical delay paths of an integrated circuit design is disclosed. The method includes predicting and ranking a set of critical delay paths based on a set of predicted-delay characteristics. Integrated circuits based on the integrated circuit design are tested to determine a set of actual delay measurements for the critical delay paths. The critical delay paths are ranked based on the actual delay measurements, and the results are correlated to the predicted ranking of critical delay paths to produce a confidence measurement that measures the likelihood that the actual critical delay paths of the design have been tested for a given production batch of devices.

Abstract: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.

Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: A lead frame (10) for a semiconductor device includes a first row of terminals (12) surrounding a die receiving area (14) and a second row of terminals (16) spaced from and surrounding the first row of terminals (12). The first and second rows of terminals (12, 16) have a first height (H1). The terminals (12) of the first row include a step (26) that has a greater height (H2). Bond wires (36) connecting die pads (34) to the first row terminals (12) extend over the second height H2 part of the terminal (12) and are attached to the first height H1 part of the terminal (12). The step (26) insures that the bond wires (36) attached to the stepped terminals (12) have a high wire kink profile so that they are less susceptible to damage in later process steps.

Abstract: A soft saturation detection circuit for a radio frequency (“RF”) power amplifier is configured to detect the onset of soft saturation in an unambiguous and accurate manner. The circuit compares the time derivative of a voltage signal indicative of the RF output power to the time derivative of a control voltage signal for the RF power amplifier. The circuit also employs a gating mechanism that ensures that a soft saturation indication signal is generated under appropriate operating conditions.

Abstract: An electrical component (100) having an inductor includes: (a) a first substrate (102) comprising at least one first electrically conductive layer (108, 110, 112); (b) one or more second substrates (104, 106) comprising at least one second electrically conductive layer (120, 132, 144); and (c) one or more electrical interconnections (124, 134, 142) electrically coupling the at least one first electrically conductive layer and the at least one second electrically conductive layer, wherein the one or more first electrically conductive layers, the one or more second electrically conductive layers and the one or more electrical interconnections are electrically coupled together to form the inductor (150).