Abstract: A device and associated method to reduce hold-time violations are disclosed. The device includes a latch module with a selectable delay. The latch module includes a control input to select the delay through the latch. In one embodiment, the delay of the latch is the time between when a latching edge of a clock signal is experienced by the latch until data changes at the output of the latch. In the event of a hold-time violation at latches that are downstream of other latches, a longer delay can be selected at an upstream latch to provide a slower delay path for data provided to the downstream latch violating the hold-time. By providing a slower delay path, the data being latched at the downstream latch will not change as quickly after a latching signal is received, and therefore the possibility of a hold-time violation is reduced.

Abstract: A non-volatile storage element disposed at an integrated circuit is disclosed. The storage element includes a first resistive element having a first magnetic tunnel junction (MTJ) element, a first node coupled to the first resistive element, a second resistive element having of a second MTJ element, a second node coupled to the second resistive element, a sense amplifier having a first input coupled to the first node, a second input coupled to the second node, and an output, and a first conductor disposed to conduct a first current to set the first resistive element to a first resistive value and the second resistive element to a second resistive value different from the first resistive value.

Abstract: A system for obtaining translation information from a data processing system transparent to the operation of a processor core of the data processing system. In one embodiment, the processor includes a processor core and memory management circuitry. The memory management circuitry stores translation information. The data processing system includes debugging circuitry for obtaining translation information stored in the memory management circuitry and for providing that information externally.

Abstract: A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on a second region of said gate dielectric, the PMOS electrode comprising a conductive metal oxide; wherein the surface of said second region of said gate dielectric comprises a material selected from the group consisting of metal oxynitrides and metal silicon-oxynitrides.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: A method of adaptively adjusting a QP of a video encoder to control output bit rate including estimating the QP based on a complexity of a previous frame and encoding bit rate information of a current frame to provide an estimated QP, determining a threshold value based on a video quality factor, a target bit rate and a complexity of a previous interval of the current frame or the same interval of the previous frame, and if the estimated QP is greater than the threshold value, adaptively adjusting the estimated QP using the threshold value, the target bit rate and the complexity of the previous interval. The method may include adaptively limiting a change of the QP between frame intervals based on a difference between the QP and the threshold value. Complexity information may be based on an average of minimum SAD values.

Abstract: A virtual address cache comprising a comparator arranged to receive a virtual address for addressing data associated with a task and a memory, wherein the comparator is arranged to make a determination as to whether data associated with the received virtual address is stored in the memory based upon an indication that the virtual address is associated with data shared between a first task and a second task and a comparison of the received virtual address with an address associated with data stored in memory.

Abstract: An enhanced tone detector including an adaptive multi-bandpass filter, a tone detector and a filter control unit. The adaptive multi-bandpass filter has a signal input receiving an input signal, a signal output providing a filtered signal, and at least one control input for receiving at least one control signal. The tone detector has an input coupled to the signal output of the adaptive multi-bandpass filter and at least one output providing at least one tone detection signal when a tone event is detected. The filter control unit has a first input receiving the input signal, at least one second input receiving the at least one tone detection signal, and at least one first output providing the at least one control signal. The control signals may include one or more frequency component signals and corresponding bandwidth signals in which the frequency component signals correspond to component frequencies of a tone event.

Abstract: A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

Abstract: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).

Abstract: A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines whether the requested translation information is present in memory management circuitry of a data processing system. If the translation information is not present in the memory management circuitry, the circuitry requests retrieval of the information by a processor core. In one embodiment, the request is performed by generating an interrupt to the processor core. In other embodiments, the request is preformed by requesting the activation of a program thread to be executed by the processor core.

Abstract: A method of generating a parameterized cell is disclosed herein. The method comprises performing a compiling interpretation on a structure layout. The compiling interpretation includes i) determining and analyzing shape relationships of the structure layout, and ii) mapping shapes and calculating properties of mapped shapes. The method also includes generating code in response to the compiling interpretation, wherein the generated code is representative of one or more parameterized cells of a pcell library of an electronic design automation software program.

Abstract: A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60) and by support structures (48) comprising a material having different etch characteristics than the materials of the spaced apart semiconductor layers. The device includes a first transistor channel (76) within the upper semiconductor layer and, in some cases, further includes a second transistor channel within the lower semiconductor layer. The resulting hybrid transistor structure may be fabricated as one of a pair of CMOS transistors, the other of which may include the same configuration or a different configuration. A method for fabricating the hybrid transistor structure includes forming a gate structure surrounding a suspended portion (52) of an upper patterned semiconductor layer (53) and extending down to a surface of a lower semiconductor layer (42).

Abstract: A reference circuit includes: (a) a first reference circuit having a reference signal and a ?VBE loop; and (b) a modification circuit using a first voltage to change a first current in the ?VBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit.

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled to the first line of memory cells; and a second power supply line coupled to the second line of memory cells. For the case where the second line of memory cells is selected for writing, a switching circuit couples the power supply terminal to the first power supply line, decouples the first power supply line from the second line of memory cells, and couples the second power supply line to the first capacitance structure. The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure. This provides more margin in the write operation on a cell in the selected line of memory cells.

Abstract: A non-volatile memory (NVM) that can be optimized for data retention or endurance is divided into portions that are optimized for one or the other or potentially some other storage characteristic. For the portion allotted for data retention, the memory cells are erased to a relatively greater extent. For the portion allotted for high endurance, the memory cells are erased to a relatively lesser extent. This is conveniently achieved by simply raising the level of the current reference that is used to determine if a cell has been sufficiently erased for the high data retention cells. The higher endurance cells thus will typically receive fewer erase pulses than the memory cells for high data retention. The reduced erasing requirement for the high endurance cells results in overall faster erasing and less stress on the high endurance cells as well as on the circuitry that generates the high erase voltages.

Abstract: A transmission line driver circuit that operates at a first voltage level is fabricated using devices that operate at a second, lower voltage level. The driver circuit includes a ramp generator that receives a speed signal and a data signal and generates a charge ramp signal and a discharge ramp signal. A pair of series connected source follower transistors have their gates connected to respective charge and discharge signal outputs of the ramp generator. The driver circuit output signal is generated at an output node between the sources of the NMOS and PMOS source follower transistors. A charge_ls generator circuit provides a charge_ls signal and a discharge_ls generator circuit provides a discharge_ls signal. A pair of protection transistors includes a first NMOS protection transistor and a first PMOS protection transistor, which are connected in series with respective ones of the source follower transistors, and their gates are connected to respective ones of the charge and discharge signals.