Abstract: An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells.

Abstract: A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

Abstract: A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.

Abstract: A low voltage detection (LVD) system for a logic device includes a first LVD circuit (110) to provide an indicator when a supply pin voltage (109) falls below a first voltage level, and a second LVD circuit (116) to provide an interrupt (118) when the supply pin voltage falls below a second voltage level. In one embodiment, the second LVD circuit consumes more power than the first LVD circuit, and is therefore selectively enabled. In one embodiment, when the supply pin voltage is between the first and second voltage levels and the logic device is in a stop or low power mode, the second LVD circuit is periodically enabled to monitor the supply pin voltage. After the supply pin voltage falls below the second voltage level, the logic device is placed in a safe state where the logic device is inhibited from acknowledging interrupts until the supply pin voltage rises above the first voltage level.

Abstract: In an input/output circuit (200), a differential balun (250) is provided that has first and second balun inputs and first and second balun outputs. An antenna (230) is connected to the first and second balun outputs. A differential amplifier (220) has one output connected to the first balun input, and a second output connected to the second balun input, while a single-ended amplifier (110) has its input connected to the first balun input. A grounding switch (240) is connected between the second balun input and ground. During a transmit mode the grounding switch (240) is open, the differential amplifier (220) is turned on, and the single-ended amplifier (110) is turned off. During a receive mode the grounding switch (240) is closed, the differential amplifier (220) is turned off, and the single-ended amplifier (110) is turned on.

Abstract: A raking receiver is provided in a wireless network. The raking receiver includes an antenna, first through Nth wavelet forming networks, first through Nth weighting mixers, a summer, a path mixer, and a signal processing circuit. The antenna receives an incoming signal. The first through Nth wavelet forming networks produce first through Nth locally generated wavelets. The first through Nth weighting mixers multiply the first through Nth locally generated wavelets by first through Nth weighting values, respectively, to produce first through Nth weighted wavelets. The summer adds together the first through Nth weighted wavelets to produce a weighted correlation input signal. The path mixer multiplies the incoming signal with the weighted correlation input signal to produce a correlated signal. And the signal processing circuit receives the correlated signal and produces a digital bit value. N is preferably an integer greater than 1.

Abstract: A processing system that interacts with external devices has a processor, a memory, and a controller. The memory stores templates that provide access protocol information about the external devices. When an external device is to be accessed, the operating system, which is stored in the memory, instructs the processor to perform the access to the external device. The processor puts the information about the external device on the address portion of the system bus where it is received and interpreted by the controller. The controller in turn retrieves the template for the external device as indicated by the information that was received. After retrieving the template, the controller outputs the information, in the manner indicated by the template, on an external interface bus where the external device is also coupled. The external device then responds according to the information that the controller put on the external interface bus.

Abstract: A wireless communication device comprises a number of sub-systems operably coupled to a data interface for routing data between the number of sub-systems. A clock generation function generates a clock signal substantially at a data transfer rate to be used over the data interface whereby the clock signal is generated at a rate that minimises harmonic content of the clock signal at operational frequencies of the wireless communication device. Thus, a suitable data rate is selected and supported by the data interface that accommodates the desired bandwidth, clock rate and/or chip rate of the functional elements that are coupled by the data interface within the wireless communication device, whilst minimising the effects of harmonic interference from the clock signal(s).

Abstract: A system and method for converting an analog signal to a digital signal is provided including a first circuit (22) having a signal range and an input for receiving a first signal, and a second circuit (24) having an input receiving the analog signal and a first output coupled to the input of the first circuit. The first circuit (22) includes an amplifier (28). The first circuit (22) samples the first signal and produces the digital signal from the first signal using the amplifier. A second output of the second circuit (24) is coupled to the amplifier (28). The second circuit (24) samples and scales the analog signal via the amplifier (28) to produce the first signal within the signal range and cancels an offset of the first signal. The system and method reduce power consumption and save device area.

Abstract: A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.

Abstract: A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save power. The gate and first terminals of the two capacitors preferably share the same conductive line such as a polysilicon segment. A second transistor and a second set of capacitors store the complementary state of the logic state so that complementary signals are provided for detecting the stored logic state. After the time for power down has ended, the state of the semiconductor storage device made up of the two transistors and four capacitors is sensed, and the detected logic state is loaded back into the latching type circuit.

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Abstract: A system and method are provided for authenticating a new device in a wireless network using an authentication device. First, the new device estimates the distance between the new device and the authenticating device as a first distance measurement, and sends the first distance measurement to the authentication device. The authentication device then estimates the distance between the new device and the authenticating device as a second distance measurement. The authentication device then evaluates the first and second distance measurements to determine if they meet authentication criteria and sends authentication data to the new device only if the first and second distance measurements meet the authentication criteria. These criteria can be that they do not differ by more than a set error value or that they both are below a set maximum value.

Abstract: A pulse width modulator (100) and method that facilitates high resolution pulse width modulation is provided. The pulse width modulator (100) creates a pulse width modulated signal having a duty cycle that is proportional to a controllable delay in the modulator. The pulse width modulator combines a first digitally controllable delay (102) with a delay adjustment (104) to provide the controllable delay. In one embodiment, a digital counter (202) is used to provide coarse delay, with the delay adjustment device (210) coupled to the digital counter (202) to provide the fine, high resolution, delay control. Together the digital counter (202) and delay adjustment device (210) provide high resolution pulse width modulation. In one particular implementation, the analog delay adjustment device (100) comprises a delay block (500) designed to provide delay adjustment that is selectively controllable by changing a capacitance in the device.

Abstract: A method is provided for sending information in a wireless network. A service data unit is broken up by a transmitter into multiple fragments that are sent as the payloads of respective data frames transmitted to a receiver. Each of these frames includes a service data unit identifier identifying the service data unit the fragment is associated with, a fragment number indicating the position of the fragment within the associated service data unit, and a total fragment value indicating the total number of fragments in the service data unit. The receiver extracts the service data unit fragments, buffers them, and uses the fragments to reconstruct the service data unit. The receiver is able to efficiently buffer the fragments because of the service data unit identifier, fragment number, and total fragment value contained in each frame.

Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

Abstract: A non-volatile memory cell and method for reading it are disclosed. In one embodiment, the non-volatile memory cell includes a fuse with a first terminal coupled to a first power supply voltage terminal, and a second terminal, a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode, and a second transistor having a first current electrode connected to the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode. By applying a read signal to the control electrode of the first transistor, the state of the cell (blown or unblown) is read.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.

Abstract: An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.