Abstract: A system on chip comprises a responder unit comprising a set of responder elements and an access control unit 484 associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result.

Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.

Abstract: A sensor circuit, comprising: at least one signal processing circuit connectable to at least one sensor operable on a channel and configured to receive and process a periodic sensor signal therefrom; a switching device coupled between the signal processing circuit and the at least one sensor, at least one switch coupled to the switching device; and a controller connected to the at least one switch and an output of the signal processing circuit. The controller is operable to re-configure the switching device via control of the switch and determine whether a short condition exists on the at least one sensor or channel based on the output from the signal processing circuit.

Abstract: A joint user detection apparatus for a wireless communication system, such as OFDM systems, arranged to account for timing impairments experienced by CAZAC codes. The proposed apparatus brings improvements over conventional receiving apparatuses by allowing joint user channel estimation processing and joint user equalization processing while considering timing impairments of user associated information present within a symbol of a received signal. The proposed solution could be used on conventional receiving apparatuses since both joint user channel estimation processing and joint user equalization processing can be activated independently such that either one or both improvements may be activated as needed or as required by the design of the conventional receiving apparatuses. A method and a computer program are also claimed.

Abstract: A power switching device includes a power terminal connected to a power supply; a load terminal connected to a load; a power switch connected between said power terminal and said load terminal and arranged to be conductive in a first operating state; a power conductor connected between said power terminal and said load terminal in at least one state, wherein an electrical current through said power conductor changes in response to said power switch being turned off, thereby causing self-induction in said power conductor; and a control unit arranged to control said power switch in real-time on the basis of a real-time level of said voltage across said power conductor so as to turn off said power switch in a continuous or stepwise or pulsed manner to prevent a voltage across said power conductor from exceeding a maximum allowed level.

Abstract: An IO driver for an integrated circuit and a method for calibrating such an IO driver are provided. The IO driver comprises a plurality of IO driver cells, a plurality of IO partial driver cells and an external resistor. The IO driver cells control IO operations for a corresponding plurality of data channels of the integrated circuit. The IO partial driver cells are coupled to respective cells of the plurality of IO driver cells. The external resistor provides a reference impedance. The reference partial driver cell is coupled to the external resistor and is arranged to determine the reference impedance and to provide information depending on the reference impedance to the IO partial driver cells. The IO partial driver cells are arranged to calibrate the respective IO driver cells based on the provided information.

Abstract: Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided.

Abstract: A packaged semiconductor device has a top and a bottom and includes a lead frame, a die, and an encapsulant that encapsulates the die and most of the lead frame. The lead frame includes a die pad on which the die is mounted, leads electrically connected to the die such as with bond wires, and die pad extensions that fan out from the die pad. Each die-pad extension has a proximal segment and a distal segment. The distal segments are interleaved with the leads. The bottoms of the die pad and the proximal segments of the extensions may be exposed at the bottom of the device. The top of the device may have notches corresponding to the extensions and portions of the distal segments may be exposed and bent into corresponding ones of the notches at the top of the device.

Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.

Abstract: A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed.

Abstract: A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

Abstract: Microelectronic packages and methods for producing microelectronic packages having sidewall-deposited heat spreader structures are provided. In one embodiment, the method includes providing a package body containing a microelectronic device. A heat spreader structure is printed or otherwise formed over at least one sidewall of the package body. The heat spreader structure is thermally coupled to the microelectronic device and is configured to dissipate heat generated thereby during operation of the microelectronic package.

Abstract: Systems and methods for production test trimming acceleration. In an illustrative, non-limiting embodiment, a method may include providing a first trim code to a reference circuit, where the reference circuit is configured to output a first signal in response to the first trim code; integrating a difference between the first signal and a target voltage value into a first integrated value; providing a second trim code to the reference circuit, where the reference circuit is configured to output a second signal in response to the second trim code; integrating a difference between the second signal and the target voltage value into a second integrated value; and adjusting at least one of the first or second trim codes in response to a comparison between the first and second integrated values.

Abstract: Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

Abstract: An electronic device is provided for determining a hopset for a frequency hopping radio communication system. The hopset is a number of radio channels in a range of channels available for radio communication, and other channels in the range constituting a channel pool of pool channels. A hopset processor assesses quality of the radio channels for communication, and removes a channel from the hopset when the assessed quality is below a predetermined threshold. A probability set is provided, the probability set having probability values for respective radio channels in the range, which probability values are adapted based on the assessed quality in the respective radio channels. A replacement channel is selected in a pseudorandom way from the channel pool weighted by the probability values, and then added to the hopset. Due to the pseudorandom selection of channels for the hopset the system can efficiently cope with various interferences.

Abstract: Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.

Abstract: A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a semiconductor die mounted on the die support area and electrically connected to the leads with bond wires. A molding material encapsulates the semiconductor die, the bond wires, and the leads, and defines a package body. The semiconductor device further includes connection bars extending vertically from the leads to a top surface of the package body. The connection bars connect the inner row leads to respective ones of the outer row leads before the molding process is performed.

Abstract: A gate drive circuit includes a first switch and a first capacitor. A first terminal of the first capacitor is electrically coupled to the first switch. The first switch is electrically coupled between the first terminal and a voltage supply of the power transistor. A second terminal of the first capacitor is electrically coupled to the reference potential. The gate drive circuit further includes a first voltage limiter in parallel with the first capacitor. The first voltage limiter limits a voltage across the first capacitor to a first predetermined voltage. The gate drive circuit further includes a second capacitor, a pre-charging circuit arranged between the first terminal of the first capacitor and a first terminal of the second capacitor. The gate drive circuit further includes a third capacitor with a first terminal electrically coupled to a second terminal of the second capacitor and a second terminal electrically coupled to a gate terminal of the power transistor.

Abstract: A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.

Abstract: A method and a computer program product for disassembling a mixed machine code are described. The machine code is provided as a sequence of code items including one or more instructions and one or more data items. The method comprises: storing the sequence of code items in accordance with a corresponding sequence of addresses; executing the machine code, thereby generating an execution trace; and partitioning the sequence of addresses into instruction address blocks and data address blocks on the basis of control data, the control data comprising at least the execution trace.