Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.

Abstract: A balun structure comprises an unbalanced input terminal, a first planar coil connected to the unbalanced input terminal, a second planar coil connected to the first planar coil, a third planar coil stacked in relation to the first planar coil, a first balanced output terminal connected to the third planar coil, a fourth planar coil stacked in relation to the second planar coil, and a second balanced output terminal connected to the fourth planar coil, wherein a first length of the first planar coil and a third length of the third planar coil differ by one twelfth to one twentieth of an operational wavelength and a second length of the second planar coil and a fourth length of the fourth planar coil differ by one twelfth to one twentieth of the operational wavelength.

Abstract: A ring oscillator circuit comprising a plurality of stages operably coupled output-to-input in a ring configuration. A frequency tuning stage comprises an inverting logic gate and a delay component. The delay component comprises a first capacitive component comprising a first terminal operably coupled to an output of the inverting logic gate and a second terminal operably coupled to a first reference voltage at least when the ring oscillator is disabled. The delay component further comprises a further capacitive component comprising a first terminal operably coupled to the output of the inverting logic gate and a second terminal selectively couplable to the first reference voltage and a second reference voltage. The second terminal of the further capacitive component is arranged to be operably coupled to the first reference voltage when the ring oscillator is enabled, and operably coupled to the second reference voltage when the ring oscillator is disabled.

Abstract: The present disclosure provides for a phase-locked loop (PLL) that includes a high-port calibration control module configured to calibrate an input modulation value of a voltage-controlled oscillator (VCO) to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency, and capture a positive frequency value of the output signal after a first accumulation time period. The high-port calibration control module is also configured to calibrate the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency, capture a negative frequency value of the output signal after a second accumulation time period, and calculate a calibration scale factor based on a difference between the positive and negative frequency values.

Abstract: The circuit generates an analog output signal which may be used to test a sigma-delta ADC. A digital waveform generator supplies a digital signal to a DAC to convert the digital signal into an analog signal. A filter filters the analog signal to obtain the analog output signal. The DAC is a DAC of a sigma-delta ADC and the filter comprises a filter of the sigma/delta ADC. A multiplexer 34 supplies the digital signal to the DAC in a generator mode wherein the circuit converts the digital signal into the analog output signal using the part of the sigma-delta ADC, or to supply a quantized analog output signal to the DAC in normal mode wherein the sigma-delta ADC converts its analog input signal into the quantized analog output signal.

Abstract: A power management circuit for integrated circuits operating systems where the power supply may be marginal includes a supply voltage characterization circuit and a clock synthesis circuit. The supply voltage characterization circuit determines the strength of the supply voltage applied to the IC and provides information to the synthesis circuit that is used to adjust the clock frequency of the IC to insure the IC does not draw too much current and force the IC into reset. A counter is used to determine the time between when the supply voltage reaches a first level and a second higher level, the time being representative of the slope of the supply voltage. Knowledge of the characteristics of a portion of the circuit under certain operating or benchmark conditions may be used to adjust the characterization.

Abstract: Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

Abstract: The invention provides an apparatus and method for checking the integrity of visual display information and has particular application to checking images displayed in an automotive vehicle, such images containing safety critical information. The image intensity is checked only to an extent commensurate with a human being able to interpret its correct meaning. Hence, images which are defective in some way yet still recognisable by the human eye are not classified as failures. In one embodiment, a part of the image containing safety critical information is segmented into smaller areas and the luminance of pixels in each segmented area is compared with a threshold brightness level and a threshold darkness level. A histogram for each area is generated and compared with a reference.

Abstract: An on-board trimming circuit suitable for trimming an accelerometer provides offset trim and gain trim modules for determining correct trim codes for subsequent programming into the trimming circuit. The correct trim codes may be determined by comparing sensor outputs which have been adjusted by successive trim codes, with a reference voltage in a comparator until the comparator toggles or by using a successive approximation technique. The reference voltage is supplied form a tap of a feedback resistance divider circuit which forms a part of an on-board voltage reference generator which may be used to provide a full scale reference for an analog to digital converter which converts a sensor output voltage into a digital signal. Using these reference voltages significantly lessens the impact of any offsets inherent in the voltage reference generator on the trimming process.

Abstract: A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die.

Abstract: A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory, a selector and a time domain transformer. The selector is configured to add at least a first list of frequency domain samples obtained for the first baseband signal to first consecutive locations in the accumulating memory centered at a first preset location associated with the first baseband signal, and a second list of frequency domain samples obtained for the second baseband signal to second consecutive locations in the accumulating memory centered at a second preset location associated with the second baseband signal. The time domain transformer is configured to apply at least an inverse discrete Fourier transform to the frequency domain samples accumulated in the accumulating memory, obtaining the aggregated baseband signal.

Abstract: An integrated matching circuits for a high frequency amplifier transistor having an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The integrated matching circuit comprises an inductive element, and a capacitive element arranged in a series arrangement with the inductive element. The series arrangement has a first terminal end connected to the input terminal or to the output terminal and a second terminal end connected to the reference terminal. The first terminal end and the second terminal end are arranged at a same lateral side of the integrated matching circuit to obtain a geometry with the first terminal end adjacent to the input terminal or to the output terminal and the second terminal end adjacent to the reference terminal.

Abstract: A method and apparatus for an orthogonal frequency division multiplexed (OFDM) communication system for communication in the presence of cyclostationary noise is provided. A receiver receives from a medium a channel measurement packet of a communication channel. The channel measurement packet has a measured transmission characteristic. The measured transmission characteristic of the received channel measurement packet is compared to a defined transmission characteristic to provide a comparison. A modulation coding scheme (MCS) map referenced to a phase of a cyclostationary noise period of the medium is generated based upon the comparison. The MCS map is sent to a transmitter via the medium. Signals including packets that have been mapped to subcarriers based on the MCS map are received from the medium. Subcarriers of the signals received from the medium are demapped using the MCS map referenced to the phase of the cyclostationary noise period of the medium.

Abstract: A method and apparatus are provided for migrating one or more hardware devices (105) associated with a virtual machine (103) from a source machine (101) to a destination machine (111) by capturing, formatting, storing, and transferring hardware context information from the hardware device(s) at the source machine during the virtual machine migration process using a defined handshake protocol at each associated hardware driver (105) to capture the hardware context information from an associated hardware device (105) being migrated.

Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

Abstract: An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.

Abstract: An antenna-diversity receiver receives data units from a transmitter in a frequency-hopping communication system. The frequency-hopping system has a channel set comprising of multiple channels, each having its own frequency range. The channel set comprises a set of multiple advertising channels and a set of multiple data channels. The receiver comprises an antenna set of multiple antennas. The transmitter has an advertising mode in which the transmitter transmits an advertising signal and switches from one advertising channel to another advertising channel in accordance with a sequence of advertising intervals, each advertising interval comprising an advertising packet. The receiver has an antenna sampling mode in which the receiver receives, successively for each combination of antenna and advertising channel, advertising packets.

Abstract: A positioning apparatus includes a support structure, a positioning structure, and a fixture for retaining MEMS devices. A shaft spans between the support structure and the positioning structure, and is configured to rotate about a first axis relative to the support structure in order to rotate the positioning structure and the fixture about the first axis. The positioning structure includes a pair of beams spaced apart by a third beam. Another shaft spans between the pair of beams and is configured to rotate about a second axis relative to the positioning structure in order to rotate the fixture about the second axis. Methodology entails installing the positioning apparatus into a chamber, orienting the fixture into various positions, and obtaining output signals from the MEMS devices to determine functionality of the MEMS devices.

Abstract: A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of grains, wherein the plurality of grains may include a bonding grain. The bonding grain may have a width substantially the same as the width of the wire bonded to the bonding pad such that no grain boundaries are present below the wire bond.