Abstract: A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

Abstract: A voltage switching system for an integrated circuit (IC) operable in first and second operational modes includes a handover module, first and second voltage regulators, a switch driver, a transistor, and a comparator. When the IC transitions between modes, the handover module receives ramp control and hand-over start signals, generates comparator and bandwidth control signals based on the hand-over start signal and a ramp signal based on the ramp control signal. The switch driver generates a power control signal based on the comparator control signal and a gate input signal based on the ramp signal. The comparator compares first and second voltage signals based on the power control signal and generates a hand-over complete signal. The handover module generates a final hand-over complete signal based on the hand-over complete signal, indicative of completion of transition between the first and second operational modes.

Abstract: Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

Abstract: A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.

Abstract: A driver circuit includes first and second pluralities of series-connected inverters for pre-driving an input signal to first and second drive transistors, and a plurality of capacitors. The first and second drive transistors coupled to the last inverter of the first and second pluralities of series-connected inverters. Each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters. In another embodiment, a plurality of discharge circuits is coupled to the first plurality of series-connected inverters. Another embodiment includes a combination of capacitors and discharge circuits coupled to the first plurality of series-connected inverters. The embodiments provide a driver circuit with high frequency voltage regulation.

Abstract: A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.

Abstract: A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature.

Abstract: The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. A switch is connected between the base of the bipolar transistor and the emitter of the bipolar transistor. A controller is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch is switched on, so as to connect the base and the emitter of the bipolar transistor.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract: A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.

Abstract: In an operation scheduler adapted to schedule in an asynchronous contention-based system a first FIFO queue is adapted to store one trigger message or one operation request. A message router is coupled to the first FIFO queue and is adapted to route instructions to a second FIFO queue or a memory and locate in the memory the instructions of a suspended operation associated with a trigger message and authorise execution of the suspended operation. An arbitration unit is coupled to the second FIFO queue and to the memory, and is adapted to schedule the execution of instructions associated with a standalone non-preemptable operation during a period of time within which at least one operation of the first sequence is being suspended.

Abstract: A circuit including and a method utilizing an improved bootstrap topology provide power to a high side (HS) driver for high efficiency applications. The improved bootstrap topology includes a transfer capacitor to store charge and to recharge a bootstrap capacitor, which provides power to the HS driver. The improved bootstrap topology also includes a resistor connected to the transfer capacitor to charge the transfer capacitor from a voltage source and to isolate the transfer capacitor from high voltage pulses.

Abstract: A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.

Abstract: A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.

Abstract: There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, control circuit, signal evaluation circuitry, a digital to analog converter, signal filters, an amplifier, demodulation circuitry and memory. The system is configured to generate high and low-frequency signals, combine them, and provide the combined input signal to a MEMS sensor. The MEMS sensor is configured to provide a modulated output signal that is a function of the combined signal. The system is configured to demodulate and filter the modulated output signal, compare the demodulated, filtered signal with the input signal to determine amplitude and phase differences, and determine, based on the amplitude and phase differences, various parameters of the MEMS sensor. A method for determining MEMS sensor parameters is also provided.

Abstract: A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

Abstract: A battery equalization circuit is provided, including: a positive battery node connecting to a positive node of a battery cell in a battery circuit with a plurality of other battery cells; a negative battery node connected to a negative node of the battery cell; a transformer winding receiving an AC voltage, the transformer winding having an upper transformer node and a tower transformer node; an upper triac connected between the positive battery node and the upper transformer node; a lower triac connected between the negative battery node and the lower transformer node; a control circuit for controlling the upper triac and the lower triac based on a measured cell voltage between the positive battery node and the negative battery node, and a total battery voltage of the battery circuit; and an isolation element connected between the control circuit and a data bus.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, a processor, measurement circuitry, stimulus circuitry and memory. The MEMS sensor is configured to provide an output responsive to physical displacement within the MEMS sensor to the measurement circuitry. The stimulus circuitry is configured to provide a stimulus signal to the MEMS sensor to cause a physical displacement within the MEMS sensor. The measurement circuitry is configured to process the output from the MEMS sensor and provide it to the processor. The processor is configured to generate stimulus signals and provide them to the stimulus circuitry for provision to the MEMS sensor. The processor is configured to monitor the output from the measurement circuitry corresponding to the physical displacement occurring in the MEMS sensor, calculate MEMS sensor characteristics based on the output, and update calibration values based on the output. Methods for monitoring and calibrating MEMS sensors are also provided.