Abstract: A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Abstract: A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.

Abstract: A small area semiconductor device package containing two or more MEMS sensor device die and a controller die for the sensor devices is provided. The controller die is mounted on top of the largest MEMS sensor device die (e.g., a gyroscope) and over a second MEMS sensor device die (e.g., an accelerometer). In one embodiment, the controller die is also mounted on the top of the second MEMS sensor device die. In another embodiment, the controller die overhangs the second MEMS sensor device die, which is of a lesser thickness than the first MEMS sensor device die.

Abstract: A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over the central core of conductive metal that is more chemically active than the conductive metal, and a second coating over the central core of conductive metal that is less chemically active than the central core of conductive metal.

Abstract: The embodiments described herein include systems with a variable reluctance sensor (VRS) interface and methods of their operation that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the VRS interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. In one embodiment the VRS interface uses a comparator with hysteresis to generate a trailing edge signal. In another embodiment the VRS interface uses bias voltages to reduce the probability of erroneous transitions in a trailing edge signal. In either case the VRS interface can prevent erroneous transitions in the detect signal and thus may improve the performance and accuracy of the system.

Abstract: A method for protecting a data item against unauthorized access and a data processing device is disclosed comprising a memory unit and a memory control unit to protect data items stored in the memory unit against prohibited access. Upon a write access the memory control unit forms a first data word comprising a data item and a first key; computes a first error-detection code; and stores the data item along with the first error-detection code. Upon a read access the memory control unit reads the data item and the first error-detection code; forms a second data word comprising the data item and a second key; computes a second error-detection code to the second data word; and determines a syndrome on the basis of the first error-detection code and the second error-detection code, wherein the syndrome is indicative of whether or not the first and second data words are identical.

Abstract: A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.

Abstract: The present disclosure provides system and method embodiments for generation of capture clock signals. A first and second test circuit receive a first test pattern and a functional clock signal. A first test clock control (TCC) circuit of the first test circuit generates a first capture clock signal that comprises a set of functional clock signal pulses generated according to a first clock pattern of the first test pattern. A second TCC circuit of the second test circuit generates a second capture clock signal that comprises the set of functional clock signal pulses generated according to the first clock pattern. The set of functional clock signal pulses of the second capture clock signal are staggered in time from the set of functional clock signal pulses of the first capture clock signal.

Abstract: The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.

Abstract: A two-input multiplexer includes first, second, and third CMOS inverters, a transmission gate, and a tri-state inverter. The first CMOS inverter receives a select signal and outputs an inverted select signal. The second CMOS inverter receives a first input signal and outputs an inverted first input signal. The transmission gate receives the select signal, the inverted first input signal, and the inverted select signal, and outputs the inverted first input signal. The tri-state inverter receives the second input signal, the inverted select signal, and the select signal, and generates an inverted second input signal. The third CMOS inverter receives one of the inverted first and second input signals, and outputs one of the first and second input signals, respectively.

Abstract: A semiconductor product comprising: a first semiconductor electrode, a second semiconductor electrode and an interconnecting semiconductor electrode defining a third semiconductor electrode; a first switch, between the first semiconductor electrode and the third semiconductor electrode, provided by a first vertical insulated-gate field-effect-transistor; and a second switch, between the second semiconductor electrode and the third semiconductor electrode, provided by a second vertical insulated-gate field-effect-transistor, wherein the interconnecting semiconductor electrode interconnects the first vertical insulated gate field-effect-transistor and the second vertical insulated gate field-effect-transistor.

Abstract: A 3D graphics system uses encryption keys to decrypt received and stored texture tiles of a texture in accordance with received and stored texture tile status data which indicates whether a texture tiles is encrypted or not and which one of the encryption keys is used. The decrypted texture tiles are rendered and at least a plurality of the rendered tiles is encrypted. The encrypted rendered tiles are stored in a frame buffer. Buffer tile status data is stored which indicates whether a rendered tile is encrypted or not before storage in the frame buffer, and which one of the encryption keys has been used. The encrypted rendered tiles stored in the frame buffer are decrypted in accordance with the buffer tile status data.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.

Abstract: An electronic control unit suitable for a motorcycle provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin and driven by a single driver circuit. In a diagnostics mode, the pin is connected to diagnostic equipment. When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp if a fault condition is detected by on-board sensors. By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.

Abstract: A method comprising: recording test code defined in a high-level test specification language; and automated analysis of the test code defined in the high-level test specification language before a conversion of the high-level test specification language to a low-level test implementation language configured to enable testing of a target by a test module.

Abstract: A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.

Abstract: A radiation device and related method are presented. The radiation device includes a body. The body includes a threaded portion configured to engage with a threaded opening in an engine and an open interior volume. The radiation device includes a ground electrode coupled to the body, a substrate disposed within the open interior volume in the body, and a radio frequency generator on the substrate. The radio frequency generator is configured to receive an input signal and, in response to the input signal, generate plasma energy between the body and the ground electrode.

Abstract: Apparatus (103) suitable for determining the resistance and inductance of an electric motor (101) estimates the phase shift between a voltage applied to the motor and motor current. Estimation of the phase shift employs a heterodyne technique. The measured motor current is conditioned prior to heterodyning in a mixer 203 in order to reduce the effects of nonlinearities introduced by a voltage source inverter (102) which supplies the motor (101) with a voltage. A value for impedance may be calculated as a ratio of a voltage applied to the motor and the motor current. The resistance and inductance may then be calculated from the impedance and phase shift calculations. In cases where the voltage applied to the motor cannot be directly measured but only the voltage supply to the voltage source inverter 102 is known, a value for impedance may be determined based on a ratio of a reconstructed voltage signal having a phase angle equal to that of the motor current and the motor current.

Abstract: A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment.