Abstract: Systems, methods, and circuits for determining one or more switch statuses are disclosed herein. In one example embodiment, such a system for determining a status of a switch having first and second terminals includes a first port configured to be coupled to the first terminal, a second port configured to be coupled to the second terminal, and a capacitor coupled between the first port and ground. Additionally, the system includes a comparator device having first and second input ports and an output port, the first input post being coupled at least indirectly to the first port, a current source coupled to the first input port, and a voltage source coupled between the second port and the second input port. The comparator device is configured to provide an output signal at the output port that is at least sometimes indicative of the status of the switch.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*In(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VTIn(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.

Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

Abstract: A dual-band Doherty amplifier and method therefor are provided. The dual-band Doherty amplifier includes a first amplifier gain element, a first transmission line coupled to a first output of the first amplifier gain element, a second amplifier gain element, a second transmission line coupled to a second output of the second amplifier gain element, and a controller configured, when a signal to be amplified is in a first band, to provide a first bias signal to a first bias input of the first amplifier gain element and a second bias signal to a second bias input of the second amplifier gain element and, when the signal is in a second band, to provide the second bias signal to the first bias input of the first amplifier gain element and the first bias signal to the second bias input of the second amplifier gain element.

Abstract: Systems, methods, and circuits for determining or more statuses are disclosed herein. In one example embodiment, such a system includes a first port configured to be coupled to a switch, a capacitor, a comparator having first and second input ports and an output port, a currant source coupled to the first input port, and a control component. The first input port is coupled to the first port and a threshold voltage is applied to the second input port. The control component is configured so that, in at least one circumstance, it causes the current source to cease driving the current in response to receiving an indication from the output post indicating that an additional voltage applied to the first input port has changed from being less than the threshold voltage to being greater than that voltage, the indication being indicative of the switch status.

Abstract: A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device against tampering is also described.

Abstract: A method, packaged semiconductor device, and system for controlling a secondary amplifier output current based on an input signal received from an amplifier input, converting electrical energy to magnetic energy at a secondary amplifier output inductor, coupling the magnetic energy from the secondary amplifier output inductor to a primary amplifier output inductor, converting the coupled magnetic energy to induced electrical energy at the primary amplifier output inductor, combining the induced electrical energy with output electrical energy from a primary amplifier gain element, and applying a combined electrical energy including the output electrical energy and the induced electrical energy to a primary amplifier load are provided.

Abstract: A compensation circuit is configured to compensate for a loss of low-frequency signal content of an input signal at a receiver input. The compensation circuit includes a switching circuit and a summing circuit coupled to the switching circuit. The switching circuit is configured to receive a first plurality of digitized values sampled from a receiver output signal. The summing circuit is configured to generate a summation signal based on a combination of a first plurality of input values selected by the switching circuit. The selecting is based on the first plurality of digitized values. The compensation circuit is configured to provide to the receiver input a compensation signal to compensate for the loss of the low-frequency signal content from the input signal. The compensation signal is based on the summation signal and is a function of at least one gain value.

Abstract: A method and apparatus are configured to receive at a control input of an analog to digital converter (ADC) circuit, from a control output of a control circuit, a first instance of control information that indicates a conversion characteristic of the ADC, wherein the conversion characteristic is one of a first conversion rate and a first conversion resolution, to provide at a status output of the ADC status information regarding the conversion of a first analog signal by the ADC circuit, to receive at the control input of the ADC a second instance of the control information that adjusts the conversion characteristic to allocate a first portion of an ADC circuit bandwidth of the ADC circuit to continuing receiving the first analog signal and to allocate a second portion of the ADC circuit bandwidth to receiving a second analog signal.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.

Abstract: A method of ganging memories in an Integrated Circuit (IC) design identifies a first subset of a first set of the memories that have word counts in a common power of two range, a common count of memory blocks, and a common column multiplexing factor, a first memory that does not have a word count in the common power of two range, a second memory of the first set of memories that does not have at least one of a common count of memory blocks and a common column multiplexing factor, and then inserts a common scrambling unit, a common chip select unit, a common comparator, a common repairing unit, a first scrambling unit, a second scrambling unit, a first comparator, and a first repairing unit into the IC design.

Abstract: A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.

Abstract: A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.

Abstract: An apparatus schedules execution of a plurality of tasks by a processor. Each task has an associated periodicity and an associated priority based upon the associated periodicity. The processor executes each of the plurality of tasks periodically according to the associated periodicity of the task. A scheduler, at each of a series of scheduling time points updates the priorities of the plurality of tasks and schedules the tasks that need to be executed in accordance with their priorities. The scheduler identifies an unexecuted task which, at a preceding scheduling time point, was scheduled for execution but which, since that preceding scheduling time point, has not been executed. The scheduler sets the priority of the unexecuted task as greater than the priority of other tasks that have the same periodicity as the unexecuted task and that are not themselves unexecuted tasks.

Abstract: A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.

Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, processing circuitry, measurement circuitry, stimulus circuitry and memory. The system is configured to provide an output responsive to physical displacement within the MEMS sensor to the measurement circuitry. The stimulus circuitry is configured to provide a stimulus signal to the MEMS sensor to cause a physical displacement within the MEMS sensor. The measurement circuitry is configured to process the output from the MEMS sensor and provide it to the processing circuitry, which is configured to generate stimulus signals and provide them to the stimulus circuitry for provision to the MEMS sensor. Output from the measurement circuitry corresponding to the physical displacement occurring in the MEMS sensor is monitored and used to calculate MEMS sensor characteristics. Methods for monitoring and calibrating MEMS sensors are also provided.