Abstract: A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that is exclusive to a particular task during a duration of time. The processor core accesses the task memory location of the local memory during the execution of the particular task, and modifies to the block of data stored in the task memory location. The extent monitor monitors a write operation the processor core to the local memory to determine a first most-extreme address of the task memory location modified by the execution of the particular task during the duration of time. The processor core also executes a write back instruction to write back to a shared memory location less than the entire block of data based upon the most-extreme address.

Abstract: A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. The protection unit contains protection data defining access rights of source units to access specified address ranges of the target memory, and a system bus interface interfacing to a source unit and a memory bus interface interfacing to the target memory via a controller. The protection unit has a control monitor for detecting an indirect memory access request, and an indirect address monitor for comparing requested address data to specified address ranges and subsequently grant the indirect memory access in accordance with access rights of the respective source unit.

Abstract: A communication apparatus for preventing the broadcasting of unauthorised messages on a broadcast bus network, the communication apparatus comprising: a first memory adapted to store first information; a second memory adapted to store second information; a monitoring unit adapted to: monitor the bus for processing messages being broadcasted on the bus, and output a third information and fourth information a comparing unit adapted to compare the first information with the third information and the second information with the fourth information; and, a message destroyer adapted to: when: the first information matches with the third information, and the second information does not match with the fourth information, causing the body of the current message to be altered while the current message is being broadcasted on the bus.

Abstract: A plurality of turbo decoder engines store extrinsic values when concurrently decoding a received signal encoded within rows and columns of an interleaving matrix where interleaved values stay in a same re-ordered row during interleaving. An extrinsic reader and extrinsic writer accesses extrinsic memories using extrinsic addresses. A deinterleaver accesses the extrinsic addressable memories by arranging storage of the extrinsic values by the same rows of the same interleaving matrix that was used to encode the received signal, each of the rows corresponding to one of the plurality of turbo decoder engines, and, in embodiments, can group the extrinsic values such that all the extrinsic values in each one of the rows of the interleaving matrix go in a same one of the plurality of the extrinsic addressable memory. The deinterleaver can skip read of extrinsic values corresponding to dummy entries in the interleaving matrix.

Abstract: A system controller controls a multi-camera view system for displaying an output image on a display. The output image is a view from a selected viewpoint. The system controller comprises an image resizing unit, a memory, and a processing unit. The image resizing unit receives the at least two input images captured by at least two cameras and is arranged to output to the memory at least two resized images, corresponding to the at least two input images, respectively. The image resizing unit resizes the at least two input images based on the selected viewpoint. The memory stores the two resized images. The processing unit is coupled to the memory and generates the output image from the at least two resized images.

Abstract: A gate drive circuit to drive a gate terminal of a power transistor. The gate drive circuit includes a first capacitor, a first switch, a measurement circuit and a reference source to generate a reference voltage. The first capacitor has a first terminal electrically coupled to the gate terminal of the power transistor. The first switch is arranged between a second terminal of the first capacitor and a first predetermined voltage. The measurement circuit is used to measure a differential voltage across the first capacitor. The gate drive circuit is configured to pre-charge the first capacitor to obtain a second predetermined voltage across the first capacitor. The gate drive circuit is further configured to arrange the first switch in an on state to turn on the power transistor and to electrically couple the first predetermined voltage to the second terminal of the first capacitor. The first capacitor is initially pre-charged at the second predetermined voltage.

Abstract: A first network node for communicating with a second network node over a first communication network is described. The second network node is arranged to communicate over the first communication network in a first part of a communication period and arranged to not communicate over the first communication network in a second part of the communication period. The first network node has a send unit for sending data formatted in data packets to the second network node, a statistics unit arranged for determining a success statistics, an availability estimator for deriving an availability estimation from the success statistics, and a send controller arranged to control the send unit in dependence on the availability estimation. Also described is a communication system, a method of estimating availability of a second network node, a method of communicating by a first network node, and an associated computer program product.

Abstract: A device is described for operating a multi-partition networking system, the device comprising hardware resources for the operation of a primary partition for performing tasks, a primary buffer for holding packets for processing within a partition of the multi-partition system and a reserve buffer. The device is arranged to allocate the primary buffer for use by the primary partition and allocate the reserve buffer for use by the primary partition when at least a suspicious condition is detected in the primary partition. A method of operating a multi-partition networking system is also described.

Abstract: A device and a method for executing a program, and a method for storing a program are described. The method of executing a program includes a sequence of instruction cycles, wherein each instruction cycle comprises: updating the program counter value; reading a data word from a memory location identified by the updated program counter value, wherein the data word comprises an instruction and a protection signature; determining a verification signature by applying a signature function associated with the program counter value to the instruction; executing the instruction if the verification signature and the protection signature are consistent with each other; and initiating an error action if they are inconsistent with each other. A method for storing a program on a data carrier is also described.

Abstract: A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.

Abstract: The present invention relates to a method and apparatus for encoding image data defining a graphics object. The method comprises partitioning the graphics object into a plurality of sub-images, deriving digital image data for each sub-image, the digital image data defining the respective sub-image, deriving sub-image position data defining the relative positioning of the sub-images within the graphics object, scrambling the digital image data for the plurality of sub-images, encrypting sub-image position data, and outputting encoded image data defining the graphics object comprising the scrambled sub-image data and the encrypted sub-image position data.

Abstract: The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.

Abstract: An enhanced digital video recording device is provided to enhance digital video recording performance, features and user experience. The recording device has a processor and a storage unit, where the storage unit has multiple computer memory units, such as SSDs, HDDs, and video transcoder for transcoding video data in a data stream. The video transcoder interacts with a controller of the storage module to differentiate between video data packets and non-video data packets of the data stream based on one or more determination criteria. Responsive to data stream being video data stream, the video transcoder transcodes the data packets of the data stream. Responsive to the data packets being encrypted, the video transcoder obtains and/or generates encryption keys and decrypts the data packets. The video transcoder also periodically provides feedback data generated from transcoding process to enhance the transcoding operations.

Abstract: A MEMS device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The MEMS device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. The second sense electrode is spaced apart from the first portion of the sense mass in a direction perpendicular to a surface of the substrate, and the second portion of the sense mass is spaced apart from the first sense electrode in the same direction. A junction is formed between the first and second portions of the sense mass so that they are coupled together and move concurrently in response to an imposed force.

Abstract: A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.

Abstract: A method for retrieving trace data from a target device is proposed. The target device comprises a program memory, a processor, a trace unit, and a trace buffer. The processor is operable to retrieve instructions from the program memory and to execute them. The trace buffer may contain trace data generated by the trace unit in response to the processor retrieving or executing instructions from the program memory. One or more patch instructions are written to the program memory. The processor executes said one or more patch instructions. The target device, in response to the processor executing said one or more patch instructions, performs a data transfer operation for copying the trace data from the trace buffer to a second memory outside the target device.

Abstract: A signal decoder in a communication system is for decoding signal elements in a communication signal having interleaved carrier frequencies. The decoder receives antenna signals in a frequency domain, and has a multiplier for multiplying the antenna signals by a complex-valued mathematical sequence such as the Zadoff-Chu sequence, to generate multiplied antenna signals. An inverse frequency to time converter converts the multiplied antenna signals to time domain signals. A signal quality detector detects a signal quality from the time domain signals based on a subset of the carrier frequencies. The complex-valued mathematical sequence is provided with zero values corresponding to carrier frequencies that are not included in the subset, and the inverse frequency to time converter has a transform size corresponding to the multiplied antenna signals including all carrier frequencies.

Abstract: A non-volatile memory device includes an array of non-volatile (NV) memory cells organized in pairs. Each pair is included with a transistor to form a memory unit. Each unit is coupled to a bit line, a word line, and a pair of source lines. The NV elements are programmable to either a relatively high resistance or relatively low resistance and the particularly resistance is established, by converting one resistance type to the other or maintaining the existing resistance type the direction of current through the NV element. A bit is formed from two NV cells in different memory units which are programmed to different resistance types and thereby provide a differential pair from which the logic state of the bit can be determined.

Abstract: A MEMS wafer (46) includes a front side (52) having a plurality of MEMS structure sites (60) at which MEMS structures (50) are located. A method (40) for protecting the MEMS structures (50) includes applying (44) a non-active feature (66) on the front side of the MEMS wafer in a region that is devoid of the MEMS structures and mounting (76) the front side of the MEMS wafer in a dicing frame (86) such that a back side (74) of the MEMS wafer is exposed. The MEMS wafer is then diced (102) from the back side into a plurality of MEMS dies (48).

Abstract: A method of forming a multilayer device includes providing a core substrate having opposing first and second core surfaces and forming top and bottom inner conductive patterns on each of the first and second core surfaces, respectively. A first dielectric layer is formed on the first core surface, and the top inner conductive pattern. A second dielectric layer is formed on the second core surface, and the bottom inner conductive pattern. The first and second dielectric layers are laminated with top and bottom outer conductive layers, respectively. A first via is provided through the core substrate extending from the top outer conductive layer to the bottom outer conductive layer. The first via is filled with solder. Magnetic particles are attracted by a magnetic force into the first via.