Abstract: An apparatus comprising: a first transmitter configured to transmit in a first channel defined by a first frequency band; a second transmitter configured to transmit in a second channel defined by a second frequency band; and a controller configured to control power transfer via the first channel in dependence upon an impedance of the first channel and an impedance of the second channel.

Abstract: An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

Abstract: The invention relates to network interface module and a method of changing network configuration parameters on-the-fly within a network device. The network interface module comprises: a processor core arranged to execute a set of threads, the set of threads comprising a port servicing thread arranged to service requests received from a network port of the network interface module; and a task scheduling component arranged to schedule the execution of threads by the processor core. The network interface module is arranged to receive an indication that at least one network configuration parameter for the network port is required to be changed, and upon receipt of such an indication to mask the port servicing thread from being executed by the processor core, and enable the at least one network parameter for the network port to be changed whilst the port servicing thread is masked.

Abstract: A proportional-to-absolute-temperature (“PTAT”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. The first and second transistors are connected to a second terminal of the bias component. The third and fourth transistors have different current densities. The first transistor is coupled to the third transistor. The second transistor is coupled to the fourth transistor. The fourth transistor and the first resistive component are coupled to a voltage common node. The output transistor has a control terminal coupled to the second and fourth transistors, a first current terminal connected to an output node, and a second current terminal coupled to the third transistor and the first resistive component. The PTAT circuit is configured to generate at least a portion of a PTAT current at the output node.

Abstract: In a video system, a video source, e.g., a camera, provides a source video stream. The source video stream comprises a stream of image data units. A buffer control unit writes the image data units consecutively to a circular buffer. A display control unit reads the image data units consecutively from the circular buffer to generate a target video stream in accordance with a read delay. The display control unit comprises a feedback loop which controls timing of the operation of reading the image data units from the circular buffer so as to reduce a difference between the read delay and a reference delay. The video system may, for example, be installed in a vehicle, e.g., for providing a driver with a live view from a camera.

Abstract: The circuit generates an analog output signal which may be used to test a sigma-delta ADC. A digital waveform generator supplies a digital signal to a DAC to convert the digital signal into an analog signal. A filter filters the analog signal to obtain the analog output signal. The DAC is a DAC of a sigma-delta ADC and the filter comprises a filter of the sigma/delta ADC. A multiplexer 34 supplies the digital signal to the DAC in a generator mode wherein the circuit converts the digital signal into the analog output signal using the part of the sigma-delta ADC, or to supply a quantized analog output signal to the DAC in normal mode wherein the sigma-delta ADC converts its analog input signal into the quantized analog output signal.

Abstract: There is provided a network interface module, and a method of implementing deterministic response frame transmission therein. The network interface module comprises a processor core arranged to execute a set of threads, the set of threads comprising at least one transmit thread arranged to cause a response frame to be transmitted upon expiry of a minimum response period from a response triggering event occurring. The network interface module further comprises a timing component arranged to output a masking timeout signal indicating expiration of successive masking timeout intervals, and a masking component arranged to mask the transmit thread from being scheduled for execution by the processing core. The masking component being further arranged to receive the masking timeout signal output by the timing component and to unmask the transmit thread upon expiry of a masking timeout interval.

Abstract: A networking device for connection to a plurality of personal area networks is described which operates according to a layer model having a PHY layer, at least a first MAC layer and a second MAC layer, and a third layer situated functionally between the PHY layer and the at least first and second MAC layers. The first and second MAC layers are arranged to support first and second protocol stacks, respectively, to access first and second respective PANs using frequency hopping spread spectrum techniques and first and second sets of parameters respectively. The first and second MAC layers are arranged to provide the first and second sets of parameters, respectively, to the third layer, which is arranged to allocate access to the PHY layer to both the first and second MAC layers in accordance with their respective sets of parameters.

Abstract: A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. The processing unit activates layers in the output image for displaying an output image on the display. The channels correspond to associated layers. The buffer controller adds to the respective fixed memory capacity of a particular buffer associated to an activated layer, one further fixed memory capacity of at least one further buffer associated to an inactive layer.

Abstract: A power regulator (1) having an output terminal (14) for providing a regulated voltage, comprising: a first control unit (35) for controlling a first operation mode, a second control unit (36) for controlling a second operation mode, a detection unit (40) connected to the output terminal (14) for detecting, at start-up, whether or not an external inductor (30) is connected to the output terminal (14), for activating the first operation mode when an external inductor (30) is detected, and for activating the second operation mode when no external inductor is detected. The detection unit (40) is further arranged for detecting in which of at least two distinct inductance ranges the inductance of the detected inductor (30) lies so as to provide inductance dependent control in the first operation mode.

Abstract: An OFDM receiving apparatus for SNR estimation of a sounding signal transmitted over a wide channel of a wireless communication system. The proposed apparatus brings improvements over conventional receiver for sounding signals by separately determining the noise power level and the signal power associated with the sounding signal. Namely, the noise power level is determined in the frequency domain based on a noise covariance matrix. Further, the sounding signal's power level is determined, in the time domain, based on power delay profile of the wide channel over which the sounding signal has been transmitted. Based on the proposed solution, required processing power, memory footprint and bus load is reduced in comparison the conventional receivers. A method and a computer program are also claimed.

Abstract: A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.

Abstract: A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.

Abstract: In a method of simulating operation of a programmable integrated circuit, a computer is operated to execute simultaneously a functional model and a timing model of the integrated circuit. Executing the functional model comprises: determining a transaction sequence which comprises one or more successive transactions of the integrated circuit and, for each transaction of said transaction sequence, updating a state of the integrated circuit in dependence of the respective transaction. Executing the timing model comprises: determining, for each of said transactions, a corresponding latency. A data carrier carrying executable instructions for instructing a computer to carry out the method and a computer system are proposed as well.

Abstract: The test signal generator generates an analog and digital test signals to test a sigma-delta ADC which has an analog portion succeeded by a digital decimation filter. The test signal generator supplies a first digital test signal having a first particular number of bits N and a first particular bit rate RN corresponding to digital signals occurring after the digital decimation filter. A digital sigma-delta modulator converts the first digital test signal into a second digital test signal having a second particular number of bits M<N thereby corresponding to a digital signal occurring at an input of the digital decimation filter. A DAC converts the second digital test signal into an analog signal, and a filter to filter the analog signal to obtain an analog test signal for testing the analog portion.

Abstract: An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

Abstract: Embodiments of packaged transducer-including devices and methods for their calibration are disclosed. Each device includes one or more transducers, an interface configured to facilitate communications with an external calibration controller, a memory, and a processing component. The external calibration controller sends calibration commands to the transducer-including devices through a communication structure. The processing component of each device executes code in response to receiving the calibration commands. Execution of the code includes generating transducer data from the one or more transducers, calculating calibration coefficients using the transducer data, and storing the calibration coefficients within the memory of the device.

Abstract: A method of decoding a received SC-FDMA symbol in a receiver in a OFDM communication system is described. The method comprises calculating an approximate constellation energy {circumflex over (K)} from channel matrices Hi for all subcarriers i, a noise covariance matrix S, and a data signal power matrix C associated with the OFDM symbol, an approximate constellation energy {circumflex over (K)}. The approximate constellation energy {circumflex over (K)} is calculated according to: Q i = H i H ? S - 1 ? H i ; Q ^ = 1 N sc ? ? i = 0 N sc - 1 ? Q i ; K ^ = diag ? ( ( Q ^ + C - 1 ) - 1 ? Q ^ ) The method further comprises decoding the received symbol using at least the associated approximate constellation energy {circumflex over (K)}. Also, a receiver, an apparatus, an OFDM communication system and a computer program product for such decoding are described.

Abstract: An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at one voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at another voltage level. At least two of the SMPA branches produce output signals having different absolute magnitudes. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.

Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.