Abstract: Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the gate. For some disclosed embodiments, a select gate is formed before a control gate. For other disclosed embodiments, the control gate is formed before the select gate. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.

Abstract: A circuit is configured for providing reverse battery protection. The circuit includes a load driver circuit having at least a first half-bridge circuit with topside and bottomside transistors coupled at a midpoint node by a first current terminal of both the topside and bottomside transistors. A second current terminal of the bottomside transistor is coupled to a voltage common node. The circuit also includes: a reverse battery protection transistor having a first current terminal coupled to a battery supply node and a second current terminal coupled to a second current terminal of the topside transistor; a bootstrap capacitor having a first terminal coupled to a the midpoint node between the topside and bottomside transistors of the first half-bridge circuit; and a diode having an anode coupled to a second terminal of the bootstrap capacitor and a cathode coupled to a control terminal of the reverse battery protection transistor.

Abstract: Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.

Abstract: The invention provides an apparatus and method which allows identification of the system which provided images for each pixel of a touchscreen display which displays merged images of arbitrary shapes supplied from a plurality of systems. It further allows routing of user inputs to the appropriate system for further processing. Colour keying may be used to superimpose one image onto another. The invention finds particular application in the automotive field where images produced by an infotainment system may be merged with those produced by a mobile phone onto the in-vehicle display screen.

Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

Abstract: A base station and method of synchronizing with a user equipment (UE) in a cell of the base station. The base station signals to the UE an indication relating to a subset of preambles chosen for synchronization with the cell from a set of preambles derivable from one or more given root sequences. The subset of preambles is chosen to provide an increased cell radius compared to the cell radius achievable if the specified full set of preambles for random access procedures was generated from the given root sequences using a given cyclic shift value.

Abstract: The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.

Abstract: A system-on-chip device comprises a core supporting a first virtual machine image and a virtual machine monitoring unit capable of communicating with the first virtual machine image. A shareable resource is also provided as well as a conflict detection unit capable of communicating with the virtual machine monitoring unit and the first virtual machine image. The conflict detection unit is arranged to detect, when in use, an access conflict caused by more than one virtual machine image attempting to access initially the shareable resource. The conflict detection unit is arranged to refer, when in use, the access conflict in response to detection thereof to the virtual machine monitoring unit for resolving of the access conflict, thereby handling the access conflict before the virtual machine monitoring unit.

Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.

Abstract: First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame.

Abstract: A converter unit for an M-order digital modulation to map L input binary sequences of N bits onto M complex values being transmitted through a communication channel, where M=2N and L and N are positive integers. The converter unit comprises an input to receive a respective input binary sequence. The converter unit is arranged to individually convert each N bits of the input binary sequence into a real number to obtain a sequence with N real numbers. The converter unit is arranged to execute complex arithmetic operations on the sequence of real numbers and to compute a respective complex value. The respective complex value corresponds to said respective input binary sequence.

Abstract: A bidirectional trench FET device includes a semiconductor substrate, a trench in the substrate extending vertically from the surface of the substrate, and a body region laterally adjacent the trench. A source region is disposed in the semiconductor substrate between the body region and the surface of the substrate. A dielectric layer is disposed over the surface and a body electrode is disposed over the dielectric layer. A body contact plug extends through the dielectric layer to interconnect the body region with the body electrode, and the body contact plug is electrically isolated from the source region. Two separate metal layers are implemented to make multiple body and source contacts electrically isolated from one another throughout the active area of the device. The low resistive path by the body contact plug and the separate metal layers enables suppression of bipolar snapback without losing bidirectional switching capability.

Abstract: There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can, for example, perform a transient simulation on the device only once, and then process the obtained signal data to add frequency spreading with specific parameters by post-processing. The resulting data can be filtered by various methods and the resulting spectrum observed. The designer can thus evaluate the reduction in electromagnetic emission level, and repeat this process by iteratively applying frequency spreading each time with specific parameters but without having to modify the schematic of the device and to perform another simulation of the device. The post-processing according to this innovation is extremely rapid as it is not a simulation process such as SPICE™, ADS™, etc. Only data is manipulated.

Abstract: An input control circuit that can be used to drive analog switches of analog modules such as an analog-to-digital converter (ADC) enables a sampling switch to receive a higher input voltage than the voltage rating of the devices comprising the sampling switch without risk of damage and without the need for a resistor divider network. The input control circuit and switch both receive an input voltage to be processed and the input control circuit generates a control signal for the switch that is derived from a pre-charged capacitor. The control circuit permits the design and manufacture of high voltage analog modules using low voltage devices, which can save on mask costs without any performance trade-offs.

Abstract: A method includes determining, for a first thread of execution, a first speculative decoded operands signal and determining, for a second thread of execution, a second speculative decoded operands signal. The method further includes determining, for the first thread of execution, a first constant and determining, for the second thread of execution, a second constant. The method further compares the first speculative decoded operands signal to the second speculative decoded operands signal and uses the first and second constant to detect a wordline collision for accessing the memory array.

Abstract: A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Abstract: There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can add frequency spreading with specific parameters by hardware. The resulting frequency spread signal can be observed. The designer can thus evaluate the reduction in electromagnetic emission level, and repeat this process by iteratively applying frequency spreading each time with specific parameters but without having to modify the design of the device and to generate another prototype of the device.

Abstract: A decoding apparatus for decoding a signal transmitted over a channel in a communication system, the signal comprising at least one data symbol and one pilot symbol the data symbol comprising a first encoded sequence encoding a transmitted sequence, the pilot symbol comprising a pilot signal. The decoding apparatus performs an additional processing after the operations of a conventional maximum likelihood decoding. A predetermined number of hypotheses of the conventional maximum likelihood decoding are selected to perform a maximum likelihood processing where channel estimation is improved by considering data symbol information. A receiver, a LTE receiver, a method and a computer program are also claimed.

Abstract: A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron.

Abstract: A wireless communication unit comprising a transmitter comprises: a linearization circuit arranged to receive and digitally distort an input signal; a radio frequency power amplifier operably coupled to the linearization circuit and arranged to amplify a radio frequency representation of the digitally distorted input signal; a feedback path arranged to feed back a portion of the amplified digitally distorted output of the received input signal to the linearization circuit; a bypass circuit comprising a plurality of energy storage elements operably coupled between an output of the radio frequency power amplifier and ground; and a first connector arranged to provide a representation of at least one electrical memory effect of at least one of the plurality of energy storage elements to the linearization circuit, wherein the linearization circuit is arranged to use the representation of the at least one electrical memory effect when digitally distorting the input signal.