Abstract: An apparatus to remove an input offset voltage of a comparator circuit includes an input voltage offset capacitor, control logic to charge and discharge the capacitor to provide an offset cancelation voltage. The offset cancellation voltage removes the input offset voltage of the comparator dependent upon an output of the comparator circuit. A switching arrangement controlled by the control logic switches signals between the capacitor and the control logic.

Abstract: A method of measuring skew between signals from an asynchronous integrated flash memory controller (IFC) includes connecting input/output (I/O) pins of the IFC to cycle based test equipment (ATE). The ATE applies a pattern of test signals as input drive to the IFC. Relative to the test cycle, the earliest delay time at which output signals from all of the I/O pins first correspond with expected results, and the latest delay time at which the output signals still correspond with the expected results are measured. The difference between the latest and the earliest delay times is compared with a limit value and a comparison report is generated.

Abstract: A memory system includes a memory and a content addressable memory (CAM). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data. The CAM includes a plurality of entries, wherein each entry configured to store an address value of an address location of the memory and one or more extended error correction bits corresponding to the data stored at the address location of the memory.

Abstract: A computer processing system includes a central processing unit (CPU) and logic instructions operable to, when a task ready to be scheduled for execution in the CPU (402) is the same as a task yielding to the task ready to be scheduled (406-Y), retain context information for the yielding task in background registers in the CPU, and move the context information for the yielding task directly from the background registers to foreground registers in the CPU for the task ready to be scheduled (410). The task ready to be scheduled is executed using the context information in the foreground registers (316).

Abstract: A capacitive touch pad includes an electrode board, a plurality of capacitive touch sensor pads, and a cover. The electrode board has touch sensor circuitry formed thereon. The plurality of capacitive touch sensor pads is formed in an array over the touch pad circuitry of the printed circuit board. The plurality of capacitive touch sensor pads is spaced apart by a predetermined distance to form spaces between the pads of the plurality of capacitive touch sensor pads. The cover is positioned over and covering substantially all of the plurality of capacitive touch sensor pads. The cover has a first cavity with a first depth, where the first cavity is shaped to form an air gap between the pads of the plurality of capacitive touch sensor pads to dampen capacitive coupling between adjacent touch pads.

Abstract: A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.

Abstract: An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.

Abstract: A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.

Abstract: A Quad Flat Non-leaded (QFN) semiconductor package has a semiconductor die mounted on a die flag of a lead frame. A molded housing with a base and sides covers the die. The package has electrically conductive mounting feet each of which includes an exposed base surface in the base of the housing, an opposite parallel surface covered by the housing, and an exposed end surface in the one of the sides of the housing. The exposed end surface is normal to, and located between, the exposed base surface and the opposite parallel surface. Bond wires selectively electrically connect electrodes of the die to respective ones of the mounting feet. An electrically conductive plating coats the exposed base portion and exposed end surface of the mounting feet.

Abstract: The invention provides a test board support platform for supporting a test board during tests, the platform comprising a heat conductive interface arranged to contact a bottom side of the test board at a first side of the heat conductive interface. The support platform also comprises a thermal conditioner coupled to a second side of the heat conductive interface, the second side being opposite the first side. By using this test board support platform a test board can be supported and thermally controlled in a way so that a DUT positioned on the test board can be probed from above, while the temperature is controlled from below.

Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

Abstract: Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: A radio frequency power amplifier comprises an input and output terminals, a main and peak amplifier stages, and an output power combiner for combining a main output signal and a peak output signal into an output signal. The output power combiner comprises a first combiner terminal electrically coupled to a main output terminal, a second combiner terminal electrically coupled to a peak output terminal, a first transition structure extending from the first combiner terminal in a first direction to a first end, a second transition structure extending from the second combiner terminal in the first direction to a second end, a first electrical conductor arranged between the first and the second ends, and a second electrical conductor arranged between the second combiner terminal and the output terminal. The first electrical conductor extends in a second direction perpendicular to the first direction. The second electrical conductor extends in the first direction.

Abstract: A front-end-of-line through-substrate via is provided for application in certain semiconductor device fabrication, including microelectromechanical (MEMS) devices. The through-substrate via (TSV) has a conductive element formed from the cylindrical core of a ring-shaped isolating etch trench. The conductivity of the core is provided by in-diffusion of dopants from a highly-doped layer deposited along sidewalls of the core within the etched trench. The highly-doped layer used as the diffusion source can be either conductive or insulating, depending upon the application. The highly-doped diffusion source layer can be retained after diffusion to further contribute to the conductivity of the TSV, to help fill or seal the via, or can be partially or completely removed. Embodiments provide for the drive in-diffusion process to use a same heating step as that used for thermal oxidation to fill or seal the via trench. Other embodiments can provide for diffusion elements from a gaseous source.

Abstract: A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

Abstract: In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it.

Abstract: A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.

Abstract: A controller system controls a plurality of lighting element arrays. The controller system comprises array selection module for selecting a lighting element array, voltage control module arranged to apply a voltage to at least the selected lighting element array, a common current source arranged to provide a current from the common current source to the selected lighting element array, and duty cycle control module arranged to control a ratio of the current to the selected lighting element array over a time sharing cycle.

Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.